MC74AC161, MC74ACT161,
MC74AC163, MC74ACT163
Synchronous Presettable
Binary Counter
The MC74AC161/74ACT161 and MC74AC163/74ACT163 are
high−speed synchronous modulo−16 binary counters. They are
synchronously presettable for application in programmable dividers
and have two types of Count Enable inputs plus a Terminal Count
output for versatility in forming synchronous multistage counters.
The MC74AC161/74ACT161 has an asynchronous Master Reset
input that overrides all other inputs and forces the outputs LOW. The
MC74AC163/74ACT163 has a Synchronous Reset input that
overrides counting and parallel loading and allows the outputs to be
simultaneously reset on the rising edge of the clock.
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16
1
DIP−16
N SUFFIX
CASE 648
•
•
•
•
•
w
Synchronous Counting and Loading
High−Speed Synchronous Expansion
Typical Count Rate of 125 MHz
Outputs Source/Sink 24 mA
′ACT161
and
′ACT163
Have TTL Compatible Inputs
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
V
CC
16
TC
15
Q
0
14
Q
1
13
Q
2
12
Q
3
11
CET
10
PE
9
16
1
SO−16
D SUFFIX
CASE 751B
16
1
EIAJ−16
M SUFFIX
CASE 966
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
1
*R
2
CP
3
P
0
4
P
1
5
P
2
6
P
3
7
CEP
8
GND
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 11 of this data sheet.
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
CEP
CET
CP
MR
SR
P
0
−P
3
PE
Q
0
−Q
3
TC
FUNCTION
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
(′161) Asynchronous Master Reset Input
(′163) Synchronous Reset Input
Parallel Data Inputs
Parallel Enable Input
Flip−Flop Outputs
Terminal Count Output
©
Semiconductor Components Industries, LLC, 2006
March, 2006
−
Rev. 7
1
Publication Order Number:
MC74AC161/D
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
operation, as shown in the Mode Select Table. A LOW
signal on MR overrides all other inputs and asynchronously
forces all outputs LOW. A LOW signal on SR overrides
counting and parallel loading and allows all outputs to go
LOW on the next rising edge of CP. A LOW signal on PE
overrides counting and allows information on the Parallel
Data (P
n
) inputs to be loaded into the flip−flops on the next
rising edge of CP. With PE and MR (′161) or SR (′163)
HIGH, CEP and CET permit counting when both are HIGH.
Conversely, a LOW signal on either CEP or CET inhibits
counting.
The MC74AC161/ACT161 and MC74AC163/ACT163 use
D−type edge−triggered flip−flops and changing the SR, PE,
CEP and CET inputs when the CP is in either state does not
cause errors, provided that the recommended setup and hold
times, with respect to the rising edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 15. To implement synchronous
multistage counters, the TC outputs can be used with the
CEP and CET inputs in two different ways. Please refer to
the MC74AC568 data sheet. The TC output is subject to
decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or
asynchronous reset for flip−flops, counters or registers.
Logic Equations:
Count Enable = CEP
•
CET
•
PE
TC = Q
0
•
Q
1
•
Q
2
•
Q
3
•
CET
0
1
2
3
4
5
6
7
11
10
9
8
PE P
0
P
1
CEP
CET
CP
*R Q
0
Q
1
P
2
P
3
TC
Q
2
Q
3
*MR for
′161
*SR for
′163
Figure 2. Logic Symbol
FUNCTIONAL DESCRIPTION
The MC74AC161/ACT161 and MC74AC163/ACT163
count modulo−16 binary sequence. From state 15 (HHHH)
they increment to state 0 (LLLL). The clock inputs of all
flip−flops are driven in parallel through a clock buffer. Thus
all changes of the Q outputs (except due to Master Reset of
the
′161)
occur as a result of, and synchronous with, the
LOW−to−HIGH transition of the CP input signal. The
circuits have four fundamental modes of operation, in order
of precedence: asynchronous reset (′161), synchronous reset
(′163), parallel load, count−up and hold. Five control inputs
−
Master Reset (MR,
′161),
Synchronous Reset (SR,
′163),
Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET)
−
determine the mode of
MODE SELECT TABLE
*SR
L
H
H
H
H
PE
X
L
H
H
H
CET
X
X
H
L
X
CEP
X
X
H
X
L
Action on the Rising
Clock Edge ( )
Reset (Clear)
Load (P
n
→
Q
n
)
Count (Increment)
No Change (Hold)
No Change (Hold)
15
14
13
12
*For
′163
only
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Figure 3. State Diagram
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2
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
P
0
PE
′161
CEP
CET
′163
ONLY
′163
P
1
P
2
P
3
TC
CP
CP
′161
ONLY
D
C
D
Q
0
CP
CP
Q
D
Q
Q
0
DETAIL A
DETAIL A
DETAIL A
DETAIL A
MR
′161
SR
′163
Q
0
Q
1
Q
2
Q
3
NOTE:
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
Figure 4. Logic Diagram
MAXIMUM RATINGS*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
T
stg
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC V
CC
or GND Current per Output Pin
Storage Temperature
Value
−0.5
to +7.0
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
±20
±50
±50
−65
to +150
Unit
V
V
V
mA
mA
mA
°C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-
mended Operating Conditions.
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3
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
t
r
, t
f
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
Input Rise and Fall Time (Note 1)
′AC
Devices except Schmitt Inputs
Input Rise and Fall Time (Note 2)
′ACT
Devices except Schmitt Inputs
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current
−
High
Output Current
−
Low
V
CC
@ 3.0 V
V
CC
@ 4.5 V
V
CC
@ 5.5 V
V
CC
@ 4.5 V
V
CC
@ 5.5 V
Parameter
′AC
′ACT
Min
2.0
4.5
0
−
−
−
−
−
−
−40
−
−
Typ
5.0
5.0
−
150
40
25
10
8.0
−
25
−
−
Max
6.0
5.5
V
CC
−
−
−
−
−
140
85
−24
24
ns/V
°C
°C
mA
mA
ns/V
Unit
V
V
t
r
, t
f
T
J
T
A
I
OH
I
OL
1. V
IN
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
IN
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
74AC
Symbol
Parameter
V
CC
(V)
T
A
= +25°C
Typ
V
IH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
−
−
−
0.002
0.001
0.001
−
−
−
−
−
−
−
74AC
T
A
=
−40°C
to
+85°C
Unit
Conditions
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
−
−
8.0
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
−75
80
V
V
OUT
= 0.1 V
or V
CC
−
0.1 V
V
OUT
= 0.1 V
or V
CC
−
0.1 V
I
OUT
=
−50
mA
V
IL
V
V
OH
V
V
*V
IN
= V
IL
or V
IH
−12
mA
I
OH
−24
mA
−24
mA
I
OUT
= 50
mA
V
V
*V
IN
= V
IL
or V
IH
12 mA
I
OL
24 mA
24 mA
V
I
= V
CC
, GND
V
OLD
= 1.65 V Max
V
OHD
= 3.85 V Min
V
IN
= V
CC
or GND
mA
mA
mA
mA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
.
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4
MC74AC161, MC74ACT161, MC74AC163, MC74ACT163
AC CHARACTERISTICS
(For Figures and Waveforms
−
See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC161
Symbol
Parameter
V
CC
*
(V)
Min
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PHL
Maximum Count
Frequency
Propagation Delay
CP to Q
n
(PE Input HIGH or LOW)
Propagation Delay
CP to Q
n
(PE Input HIGH or LOW)
Propagation Delay
CP to TC
Propagation Delay
CP to TC
Propagation Delay
CET to TC
Propagation Delay
CET to TC
Propagation Delay
MR to Q
n
Propagation Delay
MR to TC
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
70
110
2.0
1.5
1.5
1.5
3.0
2.0
3.5
2.0
2.0
1.5
2.5
2.0
2.0
1.5
3.5
2.5
T
A
= +25°C
C
L
= 50 pF
Typ
111
167
7.0
5.0
7.0
5.0
9.0
6.0
8.5
6.5
5.5
3.5
6.5
5.0
6.0
5.5
10.0
8.5
Max
−
−
12.0
9.0
12.0
9.5
15.0
10.5
14.0
11.0
9.5
6.5
11.0
8.5
12.0
9.5
15.0
13.0
74AC161
T
A
=
−40°C
to +85°C
C
L
= 50 pF
Min
60
95
1.5
1.0
1.5
1.5
2.5
1.5
2.5
2.0
1.5
1.0
2.0
1.5
1.5
1.5
3.0
2.5
Max
−
−
13.5
9.5
13.0
10.0
16.5
11.5
15.5
11.5
11.0
7.5
12.5
9.5
13.5
10.0
17.5
13.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
3−3
3−6
3−6
3−6
3−6
3−6
3−6
3−6
3−6
Unit
Fig.
No.
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
*Voltage Range 5.0 V is 5.0 V
±0.5
V.
AC CHARACTERISTICS
(For Figures and Waveforms
−
See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC163
Symbol
Parameter
V
CC
*
(V)
Min
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Count
Frequency
Propagation Delay
CP to Q
n
(PE Input HIGH or LOW)
Propagation Delay
CP to Q
n
(PE Input HIGH or LOW)
Propagation Delay
CP to TC
Propagation Delay
CP to TC
Propagation Delay
CET to TC
Propagation Delay
CET to TC
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
70
110
2.0
1.5
1.5
1.5
3.0
2.0
3.5
2.0
2.0
1.5
2.5
2.0
T
A
= +25°C
C
L
= 50 pF
Typ
95
140
7.5
5.5
8.5
6.0
9.5
7.0
11.0
8.0
7.5
5.5
8.5
6.0
Max
−
−
12.5
9.0
12.0
9.5
15.0
10.5
14.0
11.0
9.5
6.5
11.0
8.5
74AC163
T
A
=
−40°C
to +85°C
C
L
= 50 pF
Min
60
95
1.5
1.0
1.5
1.5
2.5
1.5
2.5
2.0
1.5
1.0
2.0
1.5
Max
−
−
13.5
9.5
13.0
10.0
16.5
11.5
15.5
11.5
11.0
7.5
12.5
9.5
MHz
ns
ns
ns
ns
ns
ns
3−3
3−6
3−6
3−6
3−6
3−6
3−6
Unit
Fig.
No.
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
*Voltage Range 5.0 V is 5.0 V
±0.5
V.
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