MC68HC812A4
Data Sheet
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The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
Revision
Level
Description
Figure 1-3. Expanded Wide Mode SRAM Expansion Schematic
— Figure
title changed from FLASH EEPROM to SRAM and address line designators
corrected
Figure 1-4. Expanded Narrow Mode SRAM Expansion Schematic
— Figure
title changed from FLASH EEPROM to SRAM and address line designators
corrected
4
Figure 8-16. Chip-Select Control Register 0 (CSCTL0)
— Corrected reset
value for CSPOE (bit 5)
Figure 10-1. Clock Module Block Diagram
— Corrected E- and P-clock
generator options
Figure 11-1. PLL Block Diagram
— Revised diagram to show correct
placement of divide-by-two block
12.11.2 Timer Port Data Direction Register
— Descriptive paragraph added
for clarity
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Page
Number(s)
40
42
August,
2001
(Continued
on next
page)
138
156
170
209
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor
3
Revision History
Revision History
Date
Revision
Level
Description
12.11.3 Data Direction Register for Timer Port
— Repetitive information
removed. See
12.11.2 Timer Port Data Direction Register
4
18.12 Control Timing
— Minimum values added for PW
IRQ
and PW
TIM
18.14 Non-Multiplexed Expansion Bus Timing
— Table heading changed to
reflect minimum and maximum values at 8 MHz
Table 12-3. Prescaler Selection
— Added value column and updated prescale
factors
18.11 EEPROM Characteristics
— Corrected minimum and maximum values
for programming and erase times
Figure 1-3. Expanded Wide Mode SRAM Expansion Schematic
— On sheet
1 of this schematic removed reference to resistor R2
August,
2002
6
Figure 1-4. Expanded Narrow Mode SRAM Expansion Schematic
— On
sheet 1 of this schematic removed reference to resistor R2
4.6.2 External Reset
— Corrected reference to eight E-clock cycles to nine
E-clock cycles
Updated to meet Freescale identity guidelines.
1.3 Ordering Information
— Updated
Table 1-1. Ordering Information
and
added
Figure 1-1. Device Numbering System.
Figure 1-4. Expanded Wide Mode SRAM Expansion Schematic (Sheet 1 of 3)
— Updated sheet 1 and corrected title for sheets 2 and 3.
Figure 1-5. Expanded Narrow Mode SRAM Expansion Schematic (Sheet 1 of 3)
— Updated sheet 1 and corrected title for sheets 2 and 3.
Figure 3-9. Condition Code Register (CCR)
— Corrected reset state for bit 7.
Table 4-1. Interrupt Vector Map
— Corrected reference to clock monitor reset.
4.5 Resets
— Reworked paragraph for clarity.
Figure 5-1. Mode Register (MODE)
— Changed reset state designator from
Peripheral to Special peripheral.
May,
2006
7
Figure 10-3. Clock Function Register Map
— Removed reference to Special
Reset for the COP Control Register.
Figure 10-9. COP Control Register (COPCTL)
— Corrected reset states.
12.4.1 Prescaler
— Corrected number of prescaler divides.
Figure 12-17. Timer Mask 2 Register (TMSK2)
— Corrected reset state for bit 4.
Table 16-5. ATD Interrupt Sources
— Corrected table title.
18.2 Functional Operating Range
— Corrected operating temperature range
entries.
18.10 EEPROM Characteristics
— Corrected minimum value for minimum
programming clock frequency.
18.11 Control Timing
— Corrected maximum value for frequency of operation.
18.12 Peripheral Port Timing
— Corrected table heading.
19.2 Package Dimensions
— Replaced package dimension drawing with the
latest available.
Page
Number(s)
209
329
334
197
328
40
42
77
Throughout
18
24
26
46
50
52
58
102
107
122
131
207
222
226
227
231
237
August,
2001
(Continued)
September,
2001
5
MC68HC812A4 Data Sheet, Rev. 7
4
Freescale Semiconductor
List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chapter 2 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Chapter 3 Central Processor Unit (CPU12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 4 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 5 Operating Modes and Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 6 Bus Control and Input/Output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Chapter 7 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Chapter 8 Memory Expansion and Chip-Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 9 Key Wakeups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Chapter 10 Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Chapter 11 Phase-Lock Loop (PLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Chapter 12 Standard Timer Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Chapter 13 Multiple Serial Interface (MSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Chapter 14 Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . .151
Chapter 15 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Chapter 16 Analog-to-Digital Converter (ATD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
Chapter 17 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Chapter 18 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Chapter 19 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor
5
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