Si53307
2 : 2 L
O W
J
I TT E R
U
N I V E R S A L
B
U F F E R
/ L
E V E L
T
R A N S L A T O R
Features
2 differential or 4 LVCMOS outputs
Ultra-low additive jitter: 45 fs rms
Wide frequency range: dc to
725 MHz
Any-format input with pin selectable
output formats: LVPECL, low power
LVPECL, LVDS, CML, HCSL,
LVCMOS
Synchronous output enable
2:1 input mux with glitchless input
clock switching
Independent V
DD
and V
DDO
:
1.8/2.5/3.3 V
Small size: 16-QFN (3 mm x 3 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage/Servers
Telecom
Industrial
SyncE, 1588
Backplane clock distribution
Ordering Information:
See page 27.
Pin Assignments
CLK_SEL
14
Description
The Si53307 is an ultra-low jitter two output differential buffer with pin-selectable
output clock signal format and 2:1 input clock mux. The Si53307 utilizes Silicon
Labs' advanced CMOS technology to fanout clocks from dc to 725 MHz with
guaranteed low additive jitter, low skew, and low propagation delay variability. The
Si53307 features minimal cross-talk and provides superior supply noise rejection,
simplifying low jitter clock distribution in noisy environments. Independent core
and output bank supply pins provide integrated level translation without the need
for external circuitry.
OE
GND
15
16
V
DD
CLK1
GND
SFOUT0
13
1
2
12
Q0
Q0
Q1
Q1
CLK1
3
4
5
GND
PAD
11
10
9
6
7
Functional Block Diagram
VDD
Power
Supply
Filtering
VDDO
SFOUT[1:0]
OE
Q0
Patents pending
CLK0
CLK0
Q0
CLK1
CLK1
Switching
Logic
Q1
Q1
CLK_SEL
Rev. 1.1 3/16
Copyright © 2016 by Silicon Laboratories
SFOUT1
CLK0
CLK0
V
DDO
8
Si53307
Si53307
T
ABLE O F
C
ONTENTS
Section
Page
12
13
15
15
16
16
17
17
18
21
22
24
25
27
28
29
30
30
30
31
3
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4. Synchronous Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5. Glitchless Clock Input Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7. Power Supply (V
DD
and V
DDO
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. Pin Description: 16-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1. Si53307 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 1.1
3
Si53307
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating
Temperature
Supply Voltage Range*
Symbol
T
A
V
DD
LVDS, CML
Test Condition
Min
–40
1.71
2.38
2.97
LVPECL, low power LVPECL,
LVCMOS
HCSL
Output Buffer Supply
Voltage*
V
DDO
LVDS, CML, LVCMOS
2.38
2.97
2.97
1.71
2.38
2.97
LVPECL, low power LVPECL
2.38
2.97
HCSL
*Note:
Core supply V
DD
and output buffer supplies V
DDO
are independent.
Typ
—
1.8
2.5
3.3
2.5
3.3
3.3
1.8
2.5
3.3
2.5
3.3
3.3
Max
85
1.89
2.63
3.63
2.63
3.63
3.63
1.89
2.63
3.63
2.63
3.63
3.63
Unit
°C
V
V
V
V
V
V
V
V
V
V
V
V
2.97
Table 2. Input Clock Specifications
(V
DD
=1.8 V
5%, 2.5 V
5%, or 3.3 V
10%, T
A
= –40 to 85 °C)
Parameter
Differential Input Common
Mode Voltage
Differential Input Swing
(peak-to-peak)
LVCMOS Input High Volt-
age
LVCMOS Input Low Volt-
age
Input Capacitance
Symbol
V
CM
V
IN
V
IH
V
IL
C
IN
V
DD
= 2.5 V
5%, 3.3 V
10%
V
DD
= 2.5 V
5%, 3.3 V
10%
CLK pins with respect to GND
Test Condition
Min
0.05
0.2
V
DD
x 0.7
—
—
Typ
—
—
—
—
5
Max
—
2.2
—
V
DD
x
0.3
—
Unit
V
V
V
V
pF
4
Rev. 1.1
Si53307
Table 3. DC Common Characteristics
(V
DD
= V
DDO
= 1.8 V
5%,
2.5 V
5%, or 3.3 V
10%,T
A
= –40 to 85 °C)
Parameter
Supply Current
Output Buffer
Supply Current
(Per Clock Output)
@100 MHz (diff)
@200 MHz (CMOS)
Symbol
I
DD
I
DDO
Test Condition
Min
—
Typ
65
40
35
20
60
35
5
10
20
—
Max
100
—
—
—
—
—
—
—
—
—
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
k
k
LVPECL (3.3 V)
Low Power LVPECL (3.3 V)*
LVDS (3.3 V)
CML (3.3 V)
HCSL, 100 MHz, 2 pF load
(3.3 V)
CMOS (1.8 V, SFOUTx = Open/0),
per output, C
L
= 5 pF, 200 MHz
CMOS (2.5 V, SFOUTx = Open/0),
per output, C
L
= 5 pF, 200 MHz
—
—
—
—
—
—
—
—
0.8 x VDD
CMOS (3.3 V, SFOUTx = 0/1),
per output, C
L
= 5 pF, 200 MHz
Input High Voltage
Input Mid Voltage
Input Low Voltage
Internal Pull-down
Resistor
Internal Pull-up
Resistor
V
IH
V
IM
V
IL
R
DOWN
R
UP
SFOUTx, OE, CLK_SEL
SFOUTx, 3-level input pins
SFOUTx, OE, CLK_SEL
SFOUTx, CLK_SEL
SFOUTx, OE
0.45 x VDD 0.5 x VDD 0.55 x VDD
—
—
—
—
25
25
0.2 x VDD
—
—
*Note:
Low-power LVPECL mode supports an output termination scheme that will reduce overall system power.
Rev. 1.1
5
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