74HC595-Q100; 74HCT595-Q100
Rev. 3 — 28 February 2017
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Product data sheet
1
General description
The 74HC595-Q100; 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift
register with a storage register and 3-state outputs. Both the shift and storage register
have separate clocks. The device features a serial input (DS) and a serial output (Q7S)
to enable cascading and an asynchronous reset MR input. A LOW on MR will reset
the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input.
The data in the shift register is transferred to the storage register on a LOW-to-HIGH
transition of the STCP input. If both clocks are connected together, the shift register will
always be one clock pulse ahead of the storage register. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE
causes the outputs to assume a high-impedance OFF-state. Operation of the OE input
does not affect the state of the registers. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2
Features and benefits
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
–
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
8-bit serial input
•
8-bit serial or parallel output
•
Storage register with 3-state outputs
•
Shift register with direct clear
•
100 MHz (typical) shift out frequency
•
Complies with JEDEC standard no. 7A
•
Input levels:
–
For 74HC595-Q100: CMOS level
–
For 74HCT595-Q100: TTL level
•
ESD protection:
–
MIL-STD-883, method 3015 exceeds 2000 V
–
HBM JESD22-A114F exceeds 2000 V
–
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
•
Multiple package options
3
Applications
•
Serial-to-parallel data conversion
•
Remote control holding register
Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
4
Ordering information
Package
Temperature
range
Name
SO16
SSOP16
TSSOP16
DHVQFN16
Table 1. Ordering information
Type number
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
plastic dual in-line compatible thermal
enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 × 3.5 × 0.85 mm
Version
SOT109-1
SOT338-1
SOT403-1
SOT763-1
74HC595D-Q100
74HCT595D-Q100
74HC595DB-Q100
74HCT595DB-Q100
74HC595PW-Q100
74HCT595PW-Q100
74HC595BQ-Q100
74HCT595BQ-Q100
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
5
Functional diagram
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
12 STCP
8-BIT STORAGE REGISTER
9
13 OE
3-STATE OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
15 1
2
3
4
5
6
7
mna554
Figure 1. Functional diagram
74HC_HCT595_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 28 February 2017
2 / 23
Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
13
11
12
9
15
1
2
3
4
5
6
7
12
10
11
14
R
C1/
1D
SRG8
EN3
C2
SHCP STCP
Q7S
Q0
Q1
14
Q2
DS
Q3
Q4
Q5
Q6
Q7
MR
10
OE
13
2D
3
15
1
2
3
4
5
6
7
9
mna552
mna553
Figure 2. Logic symbol
Figure 3. IEC logic symbol
STAGE 0
DS
D
FF0
CP
SHCP
MR
R
Q
D
STAGES 1 TO 6
Q
STAGE 7
D
FF7
CP
R
Q
Q7S
D
CP
STCP
OE
Q
D
CP
Q
LATCH
LATCH
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
mna555
Figure 4. Logic diagram
74HC_HCT595_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 28 February 2017
3 / 23
Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
6
Pinning information
6.1 Pinning
74HC595-Q100
74HCT595-Q100
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
aaa-003476
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
9
Q7S
74HC595-Q100
74HCT595-Q100
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
aaa-003477
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
9
Q7S
Figure 5. Pin configuration for SO16
Figure 6. Pin configuration for (T)SSOP16
74HC595-Q100
74HCT595-Q100
terminal 1
index area
Q2
Q3
Q4
Q5
Q6
Q7
2
3
4
5
6
7
8
GND
Q7S
9
GND
(1)
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
Q1
1
aaa-003478
Transparent top view
(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or
be connected to GND.
Figure 7. Pin configuration for DHVQFN16
74HC_HCT595_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 28 February 2017
4 / 23
Nexperia
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
6.2 Pin description
Table 2. Pin description
Symbol
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
GND
Q7S
MR
SHCP
STCP
OE
DS
Q0
V
CC
Pin
15, 1, 2, 3, 4, 5, 6, 7
8
9
10
11
12
13
14
15
16
Description
parallel data output
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
parallel data output 0
supply voltage
7
Functional description
[1]
Table 3. Function table
Control
SHCP STCP OE
X
X
X
↑
X
↑
X
X
L
L
H
L
Input Output
MR
L
L
L
H
Function
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance OFF-state
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
DS
X
X
X
H
Q7S
L
L
L
Q6S
Qn
NC
L
Z
NC
X
↑
↑
↑
L
L
H
H
X
X
NC
Q6S
QnS
QnS
[1]
H = HIGH voltage state;
L = LOW voltage state;
↑ = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
74HC_HCT595_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 28 February 2017
5 / 23
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
