3.3 VOLT DUAL MULTIMEDIA FIFO
DUAL 256 x 8, DUAL 512 x 8
DUAL 1,024 x 8, DUAL 2,048 x 8
DUAL 4,096 x 8
IDT72V10071, IDT72V11071
IDT72V12071, IDT72V13071
IDT72V14071
FEATURES
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•
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•
•
•
•
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Memory organization:
IDT72V10071
Dual 256 x 8
IDT72V11071
Dual 512 x 8
IDT72V12071
Dual 1,024 x 8
IDT72V13071
Dual 2,048 x 8
IDT72V14071
Dual 4,096 x 8
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
15 ns read/write cycle time
5V input tolerant
Separate control lines and data lines for each FIFO
Separate Empty and Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin plastic Thin Quad Flat Pack (STQFP)
Industrial temperature range (–40°C to +85°C)
°
°
DESCRIPTION
The IDT72V10071/72V11071/72V12071/72V13071/72V14071 are dual
Multimedia FIFOs. The device is functionally equivalent to two independent
FIFOs in a single package with all associated control, data, and flag lines
assigned to separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B) has a 8-bit input
data port (DA0 - DA7, DB0 - DB7) and a 8-bit output data port (QA0 - QA7,
QB0 - QB7). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and a Write Enable pin (WENA,
WENB).
Data is written into each of
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate Write Enable pin is asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and Read Enable pin (RENA,
RENB).
The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual clock operation. An Output Enable pin
(OEA,
OEB)
is provided on the read port of each FIFO for three-state output
control.
Each of the two FIFOs has two fixed flags, Empty (EFA,
EFB)
and Full (FFA,
FFB).
This FIFO is fabricated using IDT's high-performance submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA
WRITE
CONTROL
READ
CONTROL
RCLKA
RENA
OEA
D
A0
- D
A7
Data In
x8
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
RESET LOGIC
Q
A0
- Q
A7
Data Out
x8
FLAG OUTPUTS
RSA
EFA
FFA
WCLKB
WENB
WRITE
CONTROL
READ
CONTROL
RCLKB
RENB
OEB
D
B0
- D
B7
Data In
x8
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
Q
B0
- Q
B7
Data Out
x8
RESET LOGIC
FLAG OUTPUTS
RSB
EFB
FFB
6360 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Products specifications subject to change without notice.
NOVEMBER 2003
DSC-6360/1
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
QA
7
FFA
EFA
OEA
GND
RCLKA
RENA
GND
QB
0
QB
1
QB
2
QB
3
DNC
QB
4
QB
5
QB
6
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DA
3
GND
DA
4
DA
5
DA
6
DA
7
DNC
(1)
DNC
(1)
V
CC
WCLKB
WENB
RSB
DB
0
DB
1
DB
2
DB
3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
QA
6
QA
5
QA
4
DNC
(1)
QA
3
QA
2
QA
1
QA
0
V
CC
V
CC
WCLKA
WENA
RSA
DA
0
DA
1
DA
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
QB
7
FFB
EFB
OEB
GND
RCLKB
RENB
GND
Vcc
DNC
(1)
DNC
(1)
DB
7
DB
6
DB
5
DB
4
GND
6360 drw02
NOTE:
1. DNC = Do Not Connect.
STQFP (PP64-1, order code: TF)
TOP VIEW
2
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
The IDT72V10071/72V11071/72V12071/72V13071/72V14071's two
FIFOs, referred to as FIFO A and FIFO B, are identical in every respect.
FIFO A and FIFO B operate completely independent from each other.
Symbol
DA0-DA7
DB0-DB7
RSA, RSB
Name
A Data Inputs
B Data Inputs
Reset
I/O
I
I
I
8-bit data inputs to FIFO array A.
8-bit data inputs to FIFO array B.
When
RSA
(RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first
location;
FFA
(FFB) go as HIGH and
EFA
(EFB) go as LOW. After power-up, a reset of both FIFOs A and B
is required before an initial WRITE.
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable
is asserted.
Description
WCLKA
WCLKB
WENA
WENB
QA0-QA7
QB0-QB7
RCLKA
RCLKB
RENA
RENB
OEA
OEB
EFA
EFB
FFA
FFB
V
CC
GND
Write Clock
Write Enable
A Data Outputs
B Data Outputs
Read Clock
Read Enable
Output Enable
Empty Flag
Full Flag
Power
Ground
I
I
When
WENA
(WENB) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition WCLKA
(WCLKB). Data will not be written into the FIFO if
FFA
(FFB) is LOW.
O 8-bit data outputs from FIFO array A.
O 8-bit data outputs from FIFO array B.
I Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when
RENA
(RENB) is
asserted.
I
I
When
RENA
(RENB) is LOW, data is read from FIFO A (B) on every LOW-to-HIGH transition of RCLKA
(RCLKB). Data will not be read from Array A (B) if
EFA
(EFB) is LOW.
When
OEA
(OEB) is LOW, outputs DA0-DA7 (DB0-DB7) are active. If
OEA
(OEB) is HIGH, outputs
DA0-DA7 (DB0-DB7) will be in a high-impedance state.
O When
EFA
(EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When
EFA
(EFB) is HIGH, FIFO A (B) is not empty.
EFA
(EFB) is synchronized to RCLKA (RCLKB).
O When
FFA
(FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When
FFA
(FFB) is HIGH, FIFO A (B) is not full.
FFA
(FFB) is synchronized to WCLKA (WCLKB).
+3.3V power supply pin.
0V ground pin.
3
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage with
Respect to GND
Storage Temperature
DC Output Current
Industrial
–0.5 to +5
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
T
A
Parameter
Supply Voltage(Industrial)
Supply Voltage(Industrial)
Input High Voltage (Industrial)
Input Low Voltage (Industrial)
Operating Temperature
Industrial
Min
3.0
0
2.0
—
-40
Typ.
3.3
0
—
—
Max
3.6
—
5.0
0.8
85
Unit
V
V
V
V
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. Outputs are not 5V tolerant.
DC ELECTRICAL CHARACTERISTICS
(Industrial :V
CC
= 3.3V ± 0.3V, TA = -40°C to +85°C)
IDT72V10071
IDT72V11071
IDT72V12071
IDT72V13071
IDT72V14071
Industrial
t
CLK
= 15 ns
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC1
(3,4,5)
I
CC2
(2,6)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic “1” Voltage, I
OH
= –2 mA
Output Logic “0” Voltage, I
OL
= 8 mA
Active Power Supply Current (both FIFOs)
Standby Current
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
–1
10
—
0.4
40
10
Unit
µA
µA
V
V
mA
mA
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
OEA, OEB
≥
V
IH,
0.4
≤
V
OUT
≤
V
CC
.
3. Tested with outputs disabled (I
OUT
= 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical I
CC1
= 2[0.17 + 0.48*f
S
+ 0.02*C
L
*f
S
] (in mA).
These equations are valid under the following conditions:
V
CC
= 3.3V, T
A
= 25°C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
6. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
(2)
C
OUT
(1,2)
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
NOTE:
1. With output deselected (OEA,
OEB
≥
V
IH
).
2. Characterized values, not currently tested.
4
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(1)
(Industrial: V
CC =
3.3V± 0.3V, TA = -40°C to +85°C)
Industrial
IDT72V10071L15
IDT72V11071L15
IDT72V12071L15
IDT72V13071L15
IDT72V14071L15
Symbol
f
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSS
t
RSR
t
RSF
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
SKEW1
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Set-up Time
Data Hold Time
Enable Set-up Time
Enable Hold Time
Reset Pulse Width
(1)
Reset Set-up Time
Reset Recovery Time
Reset to Flag Time and Output Time
Output Enable to Output in Low-Z
(2)
Output Enable to Output Valid
Output Enable to Output in High-Z
Write Clock to Full Flag
Read Clock to Empty Flag
Skew Time Between Read Clock and Write Clock for Empty Flag and Full Flag
(2)
Parameter
Min.
—
2
15
6
6
4
1
4
1
15
10
10
—
0
3
3
—
—
6
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
8
10
10
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
3.3V
330Ω
D.U.T.
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
510Ω
30pF*
6360 drw03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5
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