IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 16-BIT
TRANSPARENT
LATCH
FEATURES:
IDT74FCT162373AT/CT/ET
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
≤
1μA (max.)
V
CC
= 5V ±10%
Balanced Output Drivers: ±24mA
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at V
CC
= 5V,
T
A
= 25°C
• Available in SSOP and TSSOP packages
DESCRIPTION:
The FCT162373T 16-bit transparent D-type latch is built using advanced
dual metal CMOS technology. This high-speed, low-power latch is ideal for
temporary storage of data. It can be used for implementing memory address
latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls
are organized to operate each device as two 8-bit latches, or one 16-bit latch.
Flow-through organization of signal pins simplifies layout. All inputs are designed
with hysteresis for improved noise margin.
The FCT162373T has balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall
times–reducing the need for external series terminating resistors. The
FCT162373T is a plug-in replacement for the FCT16373T and ABT16373 for
on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
1
OE
2
OE
1
LE
1
D
1
2
LE
D
1
O
1
2
D
1
D
2
O
1
C
C
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2015 Integrated Device Technology, Inc.
MARCH 2015
DSC-5455/7
IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OE
1
O
1
1
O
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SSOP/ TSSOP
TOP VIEW
V
TERM
(2)
1
LE
1
D
1
1
D
2
V
TERM
(3)
T
STG
I
OUT
GND
1
O
3
1
O
4
GND
1
D
3
1
D
4
V
CC
1
O
5
1
O
6
V
CC
1
D
5
1
D
6
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals terminals for FCT162XXX.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
GND
1
O
7
1
O
8
2
O
1
2
O
2
GND
1
D
7
1
D
8
2
D
1
2
D
2
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
xDx
Data Inputs
Latch Enable Input (Active HIGH)
Outputs Enable Input (Active LOW)
3-State Outputs
xLE
xOE
xOx
Description
GND
2
O
3
2
O
4
GND
2
D
3
2
D
4
V
CC
2
O
5
2
O
6
V
CC
2
D
5
2
D
6
FUNCTION TABLE
(1)
Inputs
xDx
H
L
X
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
Outputs
xOE
L
L
H
GND
2
O
7
2
O
8
2
OE
GND
2
D
7
2
D
8
2
LE
xLE
H
H
X
xOx
H
L
Z
2
IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
I
IL
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
V
CC
= Max.
V
I
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±1
±1
±1
±1
–1.2
–250
—
500
V
mA
mV
μA
μA
μA
Unit
V
V
μA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V
,
V
IN =
V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= 5V
,
V
IN =
V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min
I
OH
= –24mA
V
IN
= V
IH
or V
IL
V
CC
= Min
I
OL
= 24mA
V
IN
= V
IH
or V
IL
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5μA at T
A
= –55°C.
3
IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
xOE = GND
One Input Togging
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
xOE = GND
xLE = V
CC
One Bit Togging
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
xOE = GND
xLE = V
CC
Sixteen Bits Togging
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
60
Max.
1.5
100
Unit
mA
μA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
0.6
1.5
mA
—
0.9
2.3
V
IN
= V
CC
V
IN
= GND
—
2.4
4.5
(5)
V
IN
= 3.4V
V
IN
= GND
—
6.4
16.5
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZL
t
PZH
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK(o)
Parameter
Propagation Delay
xDx to xOx
Propagation Delay
xLE to xOx
Output Enable Time
Output Disable Time
Set-up Time HIGH or LOW, xDx to xLE
Hold Time HIGH or LOW, xDx to xLE
xLE Pulse Width HIGH
Output Skew
(3)
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
74FCT162373AT
Min.
(2)
Max.
1.5
5.2
2
1.5
1.5
2
1.5
5
—
8.5
6.5
5.5
—
—
—
0.5
74FCT162373CT
Min.
(2)
Max.
1.5
4.2
2
1.5
1.5
2
1.5
5
—
5.5
5.5
5
—
—
—
0.5
74FCT162373ET
Min.
(2)
Max.
1.5
3.4
1.5
1.5
1.5
1
1
3
(4)
—
3.7
4.4
3.6
—
—
—
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
5
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