4Gb Auto-AS4C256M16D3
Revision History
4Gb
Auto-AS4C256M16D3
-
96
ball FBGA PACKAGE
Revision
Rev 1.0
Rev 2.0
Details
Preliminary datasheet
1 Delete Truth Table Note 5 'Device state is 4 and 8 burst operation.'
. Add follow information in Absolute Maximum DC Ratings note2
2
'Recommended storage temperature is not exceeding 105°C. Do not
store at 150°C for more than 1000 hours.
Date
Jun
2015
Apr 2016
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
- 1/83 -
Rev.2.0 April 2016
4Gb Auto-AS4C256M16D3
Features
•
•
•
•
•
•
•
•
•
JEDEC Standard Compliant
Power supplies: V
DD
& V
DDQ
= +1.5V
±
0.075V
Operating temperature: -40~105
°
C (TC)
AEC-Q100 compliant
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 800MHz
Differential Clock, CK & CK#
Bidirectional differential data strobe
- DQS & DQS#
•
8 internal banks for concurrent operation
•
8n-bit prefetch architecture
•
Pipelined internal architecture
•
Precharge & active power down
•
Programmable Mode & Extended Mode registers
•
Additive Latency (AL): 0, CL-1, CL-2
•
Programmable Burst lengths: 4, 8
•
Burst type: Sequential / Interleave
•
Output Driver Impedance Control
•
8192 refresh cycles / 64ms
- Average refresh period
7.8µs @ -40
°
C
≦
TC
≦
+85
°
C
3.9µs @ +85
°
C
＜
TC
≦
+105
°
C
•
Write Leveling
•
ZQ Calibration
•
Dynamic ODT (Rtt_Nom & Rtt_WR)
•
RoHS compliant
•
Auto Refresh and Self Refresh
•
96-ball 9 x 13 x 1.2mm FBGA package
-
Pb and Halogen Free
Overview
The 4Gb Double-Data-Rate-3 DRAMs is double
data rate architecture to achieve high-speed operation.
It is internally configured as an eight bank DRAM.
The 4Gb chip is organized as 32Mbit x 16 I/Os x 8
bank devices. These synchronous devices achieve high
speed double-data-rate transfer rates of up to 1600 Mb/
sec/pin for general applications.
The chip is designed to comply with all key DDR3
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross point of
differential clocks (CK rising and CK# falling). All I/Os are
synchronized with differential DQS pair in a source
synchronous fashion.
These devices operate with a single 1.5V ±
0.075V power supply and are available in BGA
packages.
Table 1. Speed Grade Information
Speed Grade
DDR3-1600
Clock Frequency
800 MHz
CAS Latency
11
t
RCD
(ns)
13.75
t
RP
(ns)
13.75
Table 2. Ordering Information
Product part No
Org
Temperature
Max Clock (MHz)
800
Package
96-ball
FBGA
AS4C256M16D3-12BAN 256M x16
Automotive
-40°C
to
105°C
Confidential
- 2/83 -
Rev.2.0 April 2016
4Gb Auto-AS4C256M16D3
Figure 3. State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and the
commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die
termination, and some other events are not captured in full detail
Power
applied
Power
On
Reset
Procedure
Initialization
MRS,MPR,
Write
Leveling
E
Self
Refresh
from any
RESET
state
ZQ
Calibration
ZQCL,ZQCS
Idle
SR
ZQCL
MRS
SR
X
REF
Refreshing
PD
ACT
E
PD
X
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Active
Power
Down
PD
X
Activating
Precharge
Power
Down
PD
E
Bank
Activating
RE
ITE
Write = WR, WRS4, WRS8
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
A
W
TE
RI
AD
WR
WRITE
READ
Writing
WRITE
READ
Reading
RE
AD
A
WRITE A
READ A
IT
WR
EA
RE
AD
A
PRE, PREA
Writing
P
PR
E,
PR
EA
RE
,P
RE
A
Reading
Automatic Sequence
Command Sequence
Precharging
Confidential
- 5/83 -
Rev.2.0 April 2016
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
