DATASHEET
ISL80101-ADJ
High Performance 1A LDO
The
ISL80101-ADJ
is a low voltage, high current, single output
LDO specified at 1A output current. This LDO operates from
input voltages from 2.2V to 6V, and is capable of providing
output voltages from 0.8V to 5V. The ISL80101-ADJ features
an adjustable output. For the fixed output version of the
ISL80101-ADJ, please refer to the
ISL80101
datasheet.
A submicron BiCMOS process is utilized for this product family
to deliver the best in class analog performance and overall
value. This CMOS LDO will consume significantly lower
quiescent current as a function of load compared to bipolar
LDOs, which translates into higher efficiency and packages
with smaller footprints. State of the art internal compensation
achieves a very fast load transient response. An external
capacitor on the soft-start pin provides an adjustable
soft-starting ramp. The ENABLE feature allows the part to be
placed into a low quiescent current shutdown mode. A
Power-good logic output signals a fault condition.
Table 1
shows the differences between the ISL80101-ADJ and
others in its family:
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
ISL80101-ADJ
ISL80101
ISL80101A
ISL80121-5
PROGRAMMABLE
I
LIMIT
No
No
Yes
Yes
I
LIMIT
(DEFAULT)
1.75A
1.75A
1.62A
0.75A
ADJ OR FIXED
V
OUT
ADJ
1.8V, 2.5V,
3.3V, 5.0V
ADJ
5.0V
FN7834
Rev 3.00
August 26, 2015
Features
• ±1.8% V
OUT
accuracy guaranteed over line, load and
T
J
= -40°C to +125°C
• Very low 130mV dropout voltage at V
OUT
= 2.5V
• Very fast transient response
• Programmable soft-starting
• Power-good output
• Excellent 65dB PSRR
• Current limit protection
• Thermal shutdown function
• Available in a 10 Ld DFN package
• Pb-Free (RoHS compliant)
Applications
• DSP, FPGA and µP core power supplies
• Noise-sensitive instrumentation systems
• Post regulation of switched mode power supplies
• Industrial systems
• Medical equipment
• Telecommunications and networking equipment
• Servers
• Hard disk drives (HD/HDD)
Related Literature
•
AN1592,
“ISL80101 High Performance 1A LDO Evaluation
Board User Guide”
2.5V ± 10%
10µF
C
IN
10k
R
3
10
9
V
IN
V
IN
V
OUT
V
OUT
1
2
82pF
C
PB
3
1.00k
R
1
4
2.61k
R
2
1.8V
DROPOUT VOLTAGE (mV)
10µF
C
OUT
100k
R
PG
140
120
100
80
60
40
20
0
0
0.2
0.4
0.6
V
OUT
= 2.5V
0.8
1.0
ADJ
ISL80101-ADJ
7
6
0.01µF
C
SS
ENABLE
SS
GND
5
PG
OUTPUT CURRENT (A)
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FIGURE 2. DROPOUT vs LOAD CURRENT
FN7834 Rev 3.00
August 26, 2015
Page 1 of 12
ISL80101-ADJ
Block Diagram
V
IN
EN
CONTROL
LOGIC
-
EA
PG
THERMAL
SENSOR
REFERENCE
+
SOFT-START
+
FET DRIVER
WITH CURRENT
LIMIT
V
OUT
SS
ADJ
PG
+
-
GND
Ordering Information
PART NUMBER
(Notes
3, 4)
ISL80101IRAJZ (Note
1)
ISL80101EVAL2Z
NOTES:
1. Add “-T*” for Tape and Reel. Please refer to
TB347
for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for
ISL80101-ADJ.
For more information on MSL please see techbrief
TB363.
DZAB
Evaluation Board
PART
MARKING
V
OUT
VOLTAGE
(Note
2)
ADJ
TEMP RANGE
(°C)
-40 to +125
PACKAGE
(RoHS Compliant)
10 Ld 3x3 DFN
PKG DWG. #
L10.3x3
FN7834 Rev 3.00
August 26, 2015
Page 2 of 12
ISL80101-ADJ
Pin Configurations
ISL80101-ADJ
(10 LD 3x3 DFN)
TOP VIEW
V
OUT
1
V
OUT
2
ADJ 3
PG 4
GND 5
EPAD
10 V
IN
9 V
IN
8 NC
7 ENABLE
6 SS
Pin Descriptions
PIN NUMBER
1, 2
3
4
5
6
7
8
9, 10
-
PIN NAME
V
OUT
ADJ
PG
GND
SS
ENABLE
NC
V
IN
EPAD
DESCRIPTION
Regulated output voltage. A X5R/X7R output capacitor is required for stability. See
“External Capacitor
Requirements” on page 8
for more details.
This pin is connected to the feedback resistor divider and provides voltage feedback signals for the LDO to set the
output voltage. In addition, the PGOOD circuit uses this input to monitor the output voltage status.
This is an open-drain logic output used to indicate the status of the output voltage. Logic low indicates V
OUT
is not
in regulation. Must be grounded if not used.
Ground
External capacitor on this pin adjusts start-up ramp and controls inrush current.
V
IN
independent chip enable. TTL and CMOS compatible.
No connection; Leave floating.
Input supply; A minimum of 10µF X5R/X7R input capacitor is required for proper operation. See
“External
Capacitor Requirements” on page 8
for more details.
EPAD at ground potential. It is recommended to solder the EPAD to the ground plane.
FN7834 Rev 3.00
August 26, 2015
Page 3 of 12
ISL80101-ADJ
Absolute Maximum Ratings
V
IN
Relative to GND (Note
5)
. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
V
OUT
Relative to GND (Note
5)
. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, ADJ, SS
Relative to GND (Note
5)
. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
ESD Rating
Human Body Model (Tested per JESD22 A114F) . . . . . . . . . . . . . . .2.5kV
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 2kV
Latch-up (Tested per JESD78C, Class 2, Level A) . . . . ±100mA at +125°C
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
10 Ld DFN Package (Notes
6, 7)
. . . . . . . .
48
7
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Recommended Operating Conditions
(Notes
8, 9)
Junction Temperature Range (TJ) (Note
8)
. . . . . . . . . . . .-40°C to +125°C
V
IN
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
V
OUT
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V
PG, ENABLE, ADJ, SS relative to GND . . . . . . . . . . . . . . . . . . . . . . . 0V to 6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
6.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
7. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
8. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions
define limits where specifications are guaranteed.
9. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current.
Unless otherwise noted, 2.2V < V
IN
< 6V, V
OUT
= 0.5V, T
J
= +25°C. Applications must follow thermal guidelines
of the package to determine worst case junction temperature. Please refer to
“Applications Information” on page 8
and Tech Brief
TB379.
Boldface limits apply across the operating temperature range, -40°C to +125°C.
PARAMETER
DC CHARACTERISTICS
Feedback Pin (ADJ Option Only)
DC Input Line Regulation
V
ADJ
V
OUT
+ 0.4V < V
IN
< 6V, V
OUT
= 2.5V, 0A < I
LOAD
< 1A
491
-1
500
509
1
mV
%
SYMBOL
TEST CONDITIONS
MIN
(Note
10)
TYP
MAX
(Note
10)
UNITS
Electrical Specifications
(V
OUT
low line - V
OUT
+ 0.4V < V
IN
< 6V, V
OUT
= 2.5V
V
OUT
high
line)/V
OUT
low
line
(V
OUT
no load- 0A < I
LOAD
< 1A, V
OUT
= 2.5V
V
OUT
high
load)/ V
OUT
no
load
V
ADJ
= 0.5V
I
Q
I
SHDN
V
DO
OCP
TSD
TSDn
I
LOAD
= 0A, V
OUT
+ 0.4V < V
IN
< 6V, V
OUT
= 2.5V
I
LOAD
= 1A, V
OUT
+ 0.4V < V
IN
< 6V, V
OUT
= 2.5V
ENABLE Pin = 0.2V, V
IN
= 6V
I
LOAD
= 1A, V
OUT
= 2.5V
V
OUT
= 0V
DC Output Load Regulation
-1
1
%
Feedback Input Current
Ground Pin Current
0.01
3
5
0.2
130
1.75
160
30
1
5
7
12
212
µA
mA
mA
µA
mV
A
°C
°C
Ground Pin Current in Shutdown
Dropout Voltage (Note
11)
Output Short Circuit Current
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
AC CHARACTERISTICS
Input Supply Ripple Rejection
PSRR
f = 1kHz, I
LOAD
= 1A; V
IN
= 2.2V, V
OUT
= 1.8V
f = 120Hz, I
LOAD
= 1A; V
IN
= 2.2V, V
OUT
= 1.8V
I
LOAD
= 1A, BW = 100Hz < f < 100kHz, V
IN
= 2.2V,
V
OUT
= 1.8V
58
65
53
dB
dB
µV
RMS
Output Noise Voltage
FN7834 Rev 3.00
August 26, 2015
Page 4 of 12
ISL80101-ADJ
Unless otherwise noted, 2.2V < V
IN
< 6V, V
OUT
= 0.5V, T
J
= +25°C. Applications must follow thermal guidelines
of the package to determine worst case junction temperature. Please refer to
“Applications Information” on page 8
and Tech Brief
TB379.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
Hysteresis
ENABLE Pin Turn-on Delay
ENABLE Pin Leakage Current
SOFT-START CHARACTERISTICS
SS Pin Currents (Note
12)
IPD
ICHG
PG PIN CHARACTERISTICS
V
OUT
PG Flag Threshold
V
OUT
PG Flag Hysteresis
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
11. Dropout is defined as the difference in supply V
IN
and V
OUT
when the supply produces a 2% drop in V
OUT
from its nominal voltage.
12. I
PD
is the internal pull down current that discharges the external SS capacitor on disable. I
CHG
is the current from the SS pin that charges the external
SS capacitor during start-up.
V
IN
= 3V, I
SINK
= 500µA
V
IN
= 6V, PG = 6V
75
85
4
100
1
92
%V
OUT
%
mV
µA
V
IN
= 3.5V, ENABLE = 0V, SS = 1V
0.5
-3.3
1
-2
1.3
-0.8
mA
µA
C
OUT
= 10µF, I
LOAD
= 1A
V
IN
= 6V, ENABLE = 2.8V
0.5
10
0.8
80
100
1
1
200
V
mV
µs
µA
SYMBOL
TEST CONDITIONS
MIN
(Note
10)
TYP
MAX
(Note
10)
UNITS
Electrical Specifications
FN7834 Rev 3.00
August 26, 2015
Page 5 of 12
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