Freescale Semiconductor
Data Sheet
Document Number: MCF5485EC
Rev. 4, 12/2007
MCF548x ColdFire
®
Microprocessor
Supports MCF5480, MCF5481,
MCF5482, MCF5483, MCF5484, and
MCF5485
Features list:
• ColdFire V4e Core
– Limited superscalar V4 ColdFire processor core
– Up to 200MHz peak internal core frequency (308 MIPS
[Dhrystone 2.1] @ 200 MHz)
– Harvard architecture
– 32-Kbyte instruction cache
– 32-Kbyte data cache
– Memory Management Unit (MMU)
– Separate, 32-entry, fully-associative instruction and
data translation lookahead buffers
– Floating point unit (FPU)
– Double-precision conforms to IEE-754 standard
– Eight floating point registers
• Internal master bus (XLB) arbiter
– High performance split address and data transactions
– Support for various parking modes
• 32-bit double data rate (DDR) synchronous DRAM
(SDRAM) controller
– 66–133 MHz operation
– Supports DDR and SDR DRAM
– Built-in initialization and refresh
– Up to four chip selects enabling up to one GB of external
memory
• Version 2.2 peripheral component interconnect (PCI) bus
– 32-bit target and initiator operation
– Support for up to five external PCI masters
– 33–66 MHz operation with PCI bus to XLB divider
ratios of 1:1, 1:2, and 1:4
• Flexible multi-function external bus (FlexBus)
– Provides a glueless interface to boot flash/ROM,
SRAM, and peripheral devices
– Up to six chip selects
– 33 – 66 MHz operation
• Communications I/O subsystem
– Intelligent 16 channel DMA controller
– Up to two 10/100 Mbps fast Ethernet controllers (FECs)
each with separate 2-Kbyte receive and transmit FIFOs
– Universal serial bus (USB) version 2.0 device controller
– Support for one control and six programmable
MCF548x
TEPBGA–388
27 mm x 27 mm
•
•
•
•
•
•
•
endpoints, interrupt, bulk, or isochronous
– 4-Kbytes of shared endpoint FIFO RAM and 1 Kbyte
of endpoint descriptor RAM
– Integrated physical layer interface
– Up to four programmable serial controllers (PSCs) each
with separate 512-byte receive and transmit FIFOs for
UART, USART, modem, codec, and IrDA 1.1 interfaces
– I
2
C peripheral interface
– Two FlexCAN controller area network 2.0B controllers
each with 16 message buffers
– DMA Serial Peripheral Interface (DSPI)
Optional Cryptography accelerator module
– Execution units for:
– DES/3DES block cipher
– AES block cipher
– RC4 stream cipher
– MD5/SHA-1/SHA-256/HMAC hashing
– Random Number Generator
32-Kbyte system SRAM
– Arbitration mechanism shares bandwidth between
internal bus masters
System integration unit (SIU)
– Interrupt controller
– Watchdog timer
– Two 32-bit slice timers alarm and interrupt generation
– Up to four 32-bit general-purpose timers, compare, and
PWM capability
– GPIO ports multiplexed with peripheral pins
Debug and test features
– ColdFire background debug mode (BDM) port
– JTAG/ IEEE 1149.1 test access port
PLL and clock generator
– 30 to 66.67 MHz input frequency range
Operating Voltages
– 1.5V internal logic
– 2.5V DDR SDRAM bus I/O
– 3.3V PCI, FlexBus, and all other I/O
Estimated power consumption
– Less than 1.5W (388 PBGA)
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Table of Contents
1
2
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.1 Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .6
4.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.2 Supply Voltage Sequencing and Separation Cautions . .6
4.3 General USB Layout Guidelines . . . . . . . . . . . . . . . . . . .8
4.4 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output Driver Capability and Loading. . . . . . . . . . . . . . . . . . .10
PLL Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .12
FlexBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
8.1 FlexBus AC Timing Characteristics. . . . . . . . . . . . . . . .13
SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
9.1 SDR SDRAM AC Timing Characteristics . . . . . . . . . . .15
9.2 DDR SDRAM AC Timing Characteristics . . . . . . . . . . .18
PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Fast Ethernet AC Timing Specifications . . . . . . . . . . . . . . . . .22
11.1 MII/7-WIRE Interface Timing Specs . . . . . . . . . . . . . . .22
11.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . .23
11.3 MII Async Inputs Signal Timing (CRS, COL) . . . . . . . .24
11.4 MII Serial Management Channel Timing (MDIO,MDC).24
General Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . .25
I
2
C Input/Output Timing Specifications. . . . . . . . . . . . . . . . . .25
JTAG and Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . .26
DSPI Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . .29
Timer Module AC Timing Specifications . . . . . . . . . . . . . . . . .29
Case Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 15.DDR Clock Timing Diagram . . . . . . . . . . . . . . . . . . . .
Figure 16.DDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 17.DDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18.PCI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19.MII Receive Signal Timing Diagram. . . . . . . . . . . . . .
Figure 20.MII Transmit Signal Timing Diagram . . . . . . . . . . . . .
Figure 21.MII Async Inputs Timing Diagram . . . . . . . . . . . . . . .
Figure 22.MII Serial Management Channel TIming Diagram. . .
Figure 23.I
2
C Input/Output Timings . . . . . . . . . . . . . . . . . . . . . .
Figure 24.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . .
Figure 25.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . .
Figure 26.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . .
Figure 27.TRST Timing Debug AC Timing Specifications . . . . .
Figure 28.Real-Time Trace AC Timing . . . . . . . . . . . . . . . . . . . .
Figure 29.BDM Serial Port AC Timing . . . . . . . . . . . . . . . . . . . .
Figure 30.DSPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 31.388-pin BGA Case Outline. . . . . . . . . . . . . . . . . . . . .
18
20
21
22
23
23
24
24
26
27
27
27
27
28
28
29
31
3
4
5
6
7
8
9
10
11
List of Tables
Table 1. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . 5
Table 5. USB Filter Circuit Values . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. I/O Driver Capability . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Clock Timing Specifications. . . . . . . . . . . . . . . . . . . . . 11
Table 8. MCF548x Divide Ratio Encodings. . . . . . . . . . . . . . . . 11
Table 9. Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . 12
Table 10.FlexBus AC Timing Specifications. . . . . . . . . . . . . . . . 13
Table 11.SDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 16
Table 12.DDR Clock Crossover Specifications . . . . . . . . . . . . . 18
Table 13.DDR Timing Specifications . . . . . . . . . . . . . . . . . . . . . 18
Table 14.PCI Timing Specifications . . . . . . . . . . . . . . . . . . . . . . 21
Table 15.MII Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . 23
Table 16.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 23
Table 17.MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 24
Table 18.MII Serial Management Channel Signal Timing . . . . . 24
Table 19.General AC Timing Specifications . . . . . . . . . . . . . . . . 25
Table 20.I
2
C Input Timing Specifications between
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21. I
2
C Output Timing Specifications between
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22.JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . . 26
Table 23.Debug AC Timing Specifications . . . . . . . . . . . . . . . . . 28
Table 24.DSPI Modules AC Timing Specifications. . . . . . . . . . . 29
Table 25.Timer Module AC Timing Specifications . . . . . . . . . . . 29
12
13
14
15
16
17
18
List of Figures
Figure 1. MCF548X Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. System PLL V
DD
Power Filter . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Supply Voltage Sequencing and Separation Cautions . 7
Figure 4. Preferred VBUS Connections . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Alternate VBUS Connections . . . . . . . . . . . . . . . . . . . . 8
Figure 6. USB V
DD
Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. USBRBIAS Connection. . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Input Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . 11
Figure 9. CLKIN, Internal Bus, and Core Clock Ratios . . . . . . . 11
Figure 10.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11.FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12.FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13.SDR Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14.SDR Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MCF548x ColdFire
®
Microprocessor, Rev. 4
2
Freescale Semiconductor
ColdFire V4e Core
FPU, MMU
EMAC
32K D-cache
32K I-Cache
PLL
DDR SDRAM
Interface
FlexBus
Interface
XL Bus
Arbiter
XL
Bus
Master/Slave
Interface
Cryptography
Accelerator***
Crypto
R/W
Memory
Controller
FlexBus
Controller
Interrupt
Controller
Watchdog
Timer
Slice
Timers x 2
GP
PCI 2.2
Controller
Perpheral I/O Interface & Ports
Slave
Timers x 4
Bus
32K System
SRAM
Read
Write
DMA
DMA
XL Bus
Read/Write
FlexCAN
x2
Multi-Channel DMA
Master Bus Interface & FIFOs
CommBus
PCI Interface
& FIFOs
DSPI
I
2
C
PSC x 4
FEC1
FEC2**
USB 2.0
DEVICE*
Perpheral Communications I/O Interface & Ports
USB 2.0
PHY*
Figure 1. MCF548X Block Diagram
MCF548x ColdFire
®
Microprocessor, Rev. 4
Freescale Semiconductor
3
PCI I/O Interface & Ports
Communications
I/O Subsystem
System
Integration Unit
Maximum Ratings
1
Maximum Ratings
Table 1. Absolute Maximum Ratings
Rating
External (I/O pads) supply voltage (3.3-V power pins)
Internal logic supply voltage
Memory (I/O pads) supply voltage (2.5-V power pins)
PLL supply voltage
Internal logic supply voltage, input voltage level
Storage temperature range
Symbol
EV
DD
IV
DD
SD V
DD
PLL V
DD
V
in
T
stg
Value
–0.3 to +4.0
–0.5 to +2.0
–0.3 to +4.0 SDR Memory
–0.3 to +2.8 DDR Memory
–0.5 to +2.0
–0.5 to +3.6
–55 to +150
Units
V
V
V
V
V
o
C
Table 1
lists maximum and minimum ratings for supply and operating voltages and storage temperature. Operating outside of
these ranges may cause erratic behavior or damage to the processor.
2
2.1
Thermal Characteristics
Operating Temperatures
Table 2. Operating Temperatures
Characteristic
Maximum operating junction temperature
Maximum operating ambient temperature
Minimum operating ambient temperature
1
Table 2
lists junction and ambient operating temperatures.
Symbol
T
j
T
Amax
T
Amin
Value
105
<85
1
–40
Units
o
C
o
C
o
C
This published maximum operating ambient temperature should be used only as a system design guideline. All device
operating parameters are guaranteed only when the junction temperature lies within the specified range.
MCF548x ColdFire
®
Microprocessor, Rev. 4
4
Freescale Semiconductor
DC Electrical Specifications
2.2
Thermal Resistance
Table 3. Thermal Resistance
Characteristic
324 pin TEPBGA — Junction to ambient, natural
convection
388 pin TEPBGA — Junction to ambient, natural
convection
Junction to ambient (@200 ft/min)
Junction to board
Junction to case
Junction to top of package
Four layer board (2s2p)
Four layer board (2s2p)
Four layer board (2s2p)
—
—
Natural convection
Symbol
θ
JMA
θ
JMA
θ
JMA
θ
JB
θ
JC
Ψ
jt
Value
20–22
1,2
19
1,2
16
1,2
11
3
7
4
2
1,5
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Table 3
lists thermal resistance values.
1
2
3
4
5
θ
JA
and
Ψ
jt
parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection. Freescale
recommends the use of
θ
JA
and power dissipation specifications in the system design to prevent device junction
temperatures from exceeding the rated specification. System designers should be aware that device junction
temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device
junction temperature specification can be verified by physical measurement in the customer’s system using the
Ψ
jt
parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
Per JEDEC JESD51-6 with the board horizontal.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
3
DC Electrical Specifications
Table 4
lists DC electrical operating temperatures. This table is based on an operating voltage of EV
DD
= 3.3 V
DC
± 0.3 V
DC
and IV
DD
of 1.5 ± 0.07 V
DC
.
Table 4. DC Electrical Specifications
Characteristic
External (I/O pads) operation voltage range
Memory (I/O pads) operation voltage range (DDR Memory)
Internal logic operation voltage range
1
PLL Analog operation voltage range
1
USB oscillator operation voltage range
USB digital logic operation voltage range
USB PHY operation voltage range
USB oscillator analog operation voltage range
Symbol
EV
DD
SD V
DD
IV
DD
PLL V
DD
USB_OSV
DD
USBV
DD
USB_PHYV
DD
USB_OSCAV
DD
Min
3.0
2.30
1.43
1.43
3.0
3.0
3.0
1.43
Max
3.6
2.70
1.58
1.58
3.6
3.6
3.6
1.58
Units
V
V
V
V
V
V
V
V
MCF548x ColdFire
®
Microprocessor, Rev. 4
Freescale Semiconductor
5
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