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NLSF302MNR2

产品描述Logic Gates LOG QUAD 2-INPUT NOR
产品类别逻辑    逻辑   
文件大小65KB,共4页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
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NLSF302MNR2概述

Logic Gates LOG QUAD 2-INPUT NOR

NLSF302MNR2规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称ON Semiconductor(安森美)
零件包装代码QFN
包装说明QFN-16
针数16
Reach Compliance Codenot_compliant
Factory Lead Time1 week
系列302
JESD-30 代码S-XQCC-N16
JESD-609代码e0
长度3 mm
负载电容(CL)50 pF
逻辑集成电路类型NOR GATE
最大I(ol)0.00005 A
功能数量4
输入次数2
端子数量16
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料UNSPECIFIED
封装代码HVQCCN
封装等效代码LCC16,.12SQ,20
封装形状SQUARE
封装形式CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法TAPE AND REEL
峰值回流温度(摄氏度)240
电源2.5/5 V
Prop。Delay @ Nom-Sup13 ns
传播延迟(tpd)13 ns
认证状态Not Qualified
施密特触发器NO
座面最大高度1 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)2 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn90Pb10)
端子形式NO LEAD
端子节距0.5 mm
端子位置QUAD
处于峰值回流温度下的最长时间30
宽度3 mm

文档预览

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NLSF302
Quad 2−Input NOR Gate
The NLSF302 is an advanced high speed CMOS 2−input NOR gate
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
http://onsemi.com
FUNCTION TABLE
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
H
L
L
L
NLSF302 = Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NLSF302MNR2
NLSF302MNR2G
Package
QFN−16
QFN−16
(Pb−Free)
Shipping
3000/Tape & Reel
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
May, 2006 − Rev. 4
ÇÇÇ
ÇÇÇ
ÇÇÇ
High Speed: t
PD
= 3.6 ns (Typ) at V
CC
= 5.0 V
Low Power Dissipation: I
CC
= 2.0
mA
(Max) at T
A
= 25°C
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: V
OLP
= 0.8 V (Max)
Function Compatible with Other Standard Logic Families
QFN−16 Package
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Machine Model > 200 V
Chip Complexity: 40 FETs or 10 Equivalent Gates
Pb−Free Package is Available*
1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM
16
1
NLSF
302
ALYW
G
G
Publication Order Number:
NLSF302/D

 
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