Intel® Atom™ Processor S1200
Product Family for Microserver
Datasheet
,
Volume 1 of 2
December 2012
Document Number: 328194-001
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Intel® Atom™ Processor S1200 Product Family for Microserver
Datasheet—Volume 1 of 2
2
December 2012
Document Number: 328194-001
Revision History
Date
November 2012
Revision
1.0
Description
Initial release.
December 2012
Document Number: 328194-001
Intel® Atom™ Processor S1200 Product Family for Microserver
Datasheet—Volume 1 of 2
3
Contents
1
Overview
.................................................................................................................. 9
1.1
Introduction ....................................................................................................... 9
1.2
Key Features of the Processor .............................................................................11
1.2.1 Intel® Atom™ Core Features and Caching Hierarchy ...................................13
1.2.1.1 Processor Core Technologies .......................................................13
1.2.2 UnCore Features.....................................................................................14
1.2.2.1 Integrated Memory Controller (iMC).............................................14
1.2.2.2 Integrated I/O (IIO) .................................................................14
1.2.3 Legacy I/O Features................................................................................16
1.3
Power Management Support................................................................................17
1.3.1 Power Management Features....................................................................17
1.4
Thermal Management Support.............................................................................18
1.5
Package Summary .............................................................................................18
1.6
Terminology......................................................................................................19
1.7
Related Documents ............................................................................................21
1.8
State of Data ....................................................................................................21
Interfaces
................................................................................................................22
2.1
Integrated Memory Controller..............................................................................22
2.1.1 Introduction ...........................................................................................22
2.1.2 Supported Features.................................................................................22
2.1.3 Functional Description .............................................................................23
2.1.3.1 DRAM Requests and Data Ordering ..............................................23
2.1.3.2 DRAM Out of Bound Access.........................................................23
2.1.3.3 DRAM Power Management ..........................................................24
2.2
PCI Express Interface .........................................................................................26
2.2.1 PCI Express Root Port Features and Functions ............................................26
2.2.2 PCI Express Architecture..........................................................................27
2.2.2.1 Transaction Layer......................................................................27
2.2.2.2 Data Link Layer.........................................................................28
2.2.2.3 Physical Layer...........................................................................28
2.2.3 PCI Express Configuration Mechanism .......................................................28
2.3
SMBus..............................................................................................................29
2.3.1 System Management...............................................................................29
2.4
Integrated Legacy I/O Overview ..........................................................................30
2.4.1 High-Speed UART (HSUART) ....................................................................32
2.4.2 Low Pin Count (LPC) Interface ..................................................................33
2.4.3 Internal CPU Interface Signals ..................................................................33
2.4.3.1 CPU Interface Signal - INIT# ......................................................33
2.4.3.2 CPU Interface Signal - NMI .........................................................33
2.4.3.3 CPU Interface Signal - INTR ........................................................33
2.4.3.4 CPU Interface Signal - SMI# .......................................................33
2.4.4 I/O Advanced Programmable Interrupt Controller (IOxAPIC).........................33
2.4.5 General-Purpose I/O (GPIO).....................................................................34
2.4.6 Serial Peripheral Interface (SPI) ...............................................................34
2.4.7 Real Time Clock......................................................................................35
2.4.8 8254 Programmable Interval Timer (PIT) ...................................................36
2.4.8.1 Counter 0, System Timer ...........................................................36
2.4.8.2 Counter 1, Refresh-Cycle Toggle Status........................................36
2.4.8.3 Counter 2, Speaker Tone............................................................36
2.4.8.4 Timer I/O Registers ...................................................................37
2.4.9 8259 Interrupt Controllers (PIC) ...............................................................38
2.4.9.1 I/O Registers ............................................................................39
2
Intel® Atom™ Processor S1200 Product Family for Microserver
Datasheet—Volume 1 of 2
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December 2012
Document Number: 328194-001
2.4.10 High-Precision Event Timer (HPET) ........................................................... 40
2.4.10.1 HPET MMIO Registers ................................................................ 40
2.4.11 SMBus 1.0 Controller .............................................................................. 41
2.4.12 System Audio Speaker ............................................................................ 41
2.4.13 Watchdog Timer (WDT)........................................................................... 42
2.4.13.1 Features .................................................................................. 42
3
Technologies
........................................................................................................... 43
3.1
Intel® Virtualization Technology (Intel® VT) ........................................................ 43
3.1.1 Intel VT-x Objectives .............................................................................. 43
3.1.2 Intel VT-x Features................................................................................. 44
3.2
Security Technologies ........................................................................................ 45
3.2.1 Execute Disable Bit................................................................................. 45
3.3
Intel® Hyper-Threading Technology .................................................................... 45
3.4
Enhanced Intel SpeedStep® Technology .............................................................. 46
Power Management
................................................................................................. 47
4.1
Overview ......................................................................................................... 47
4.1.1 Acronyms.............................................................................................. 48
4.1.2 Power Management Features ................................................................... 49
4.2
Communication with the External Circuitry............................................................ 50
4.3
Power Planes and Voltage Rails ........................................................................... 52
4.3.1 Power Group Definitions .......................................................................... 52
4.3.1.1 Core Power Well ....................................................................... 52
4.3.1.2 SUS Power Well ........................................................................ 53
4.3.1.3 RTC Power Well ........................................................................ 53
4.3.2 Power Plane vs. Supported System Sleep States......................................... 54
4.3.3 Voltage Sequencing Requirements ............................................................ 54
4.3.4 Voltage Rail Ramp Rate........................................................................... 55
4.3.5 SerialVID (SVID) Overview ...................................................................... 55
4.4
ACPI State Descriptions...................................................................................... 56
4.5
Performance States (P-States) and Throttling........................................................ 58
4.5.1 Enhanced Intel SpeedStep
®
Technology ................................................... 58
4.5.2 Dynamic Power Management on I/O ......................................................... 59
4.5.2.1 LPC Clock Control ..................................................................... 59
4.6
Processor Core States (C-State) .......................................................................... 60
4.6.1 C-State Variations .................................................................................. 61
4.6.2 C-State Definition................................................................................... 62
4.6.2.1 C0 State – Full On..................................................................... 62
4.6.2.2 C1 State – Auto-Halt ................................................................. 62
4.6.2.3 C2 State – Stop Grant ............................................................... 62
4.6.2.4 C4 State – Deeper Sleep............................................................ 63
4.6.2.5 C6 - Deep Power Down Technology ............................................. 64
4.6.2.6 C6 Demotion Policy ................................................................... 64
4.6.3 Extended Low Power States ..................................................................... 65
4.6.4 C2 Popup/Popdown................................................................................. 66
4.6.5 Recommended C-State Configurations ...................................................... 66
4.6.6 Hardware Coordination of C-States ........................................................... 67
4.6.7 I/O Based C-State Hardware Coordination ................................................. 68
4.6.8 C-States from I/O Instruction Decoded to MWAIT ....................................... 68
4.6.9 C1 BIOS Coordination ............................................................................. 68
4.6.10 CPU C-State Triggering ........................................................................... 69
4.7
Transition Rules Among C States and S States ...................................................... 70
4.8
System Sleep State Control (S States) ................................................................. 71
4.8.1 S-State Definition................................................................................... 71
4.8.1.1 S0 - Full On ............................................................................. 71
4
December 2012
Document Number: 328194-001
Intel® Atom™ Processor S1200 Product Family for Microserver
Datasheet—Volume 1 of 2
5
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