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74LVC2G00DC-Q100H

产品描述Logic Gates 74LVC2G00DC-Q100/VSSOP8/REEL 7
产品类别半导体    逻辑   
文件大小746KB,共12页
制造商NXP(恩智浦)
官网地址https://www.nxp.com
标准
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74LVC2G00DC-Q100H概述

Logic Gates 74LVC2G00DC-Q100/VSSOP8/REEL 7

74LVC2G00DC-Q100H规格参数

参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
NXP(恩智浦)
产品种类
Product Category
Logic Gates
RoHSDetails
安装风格
Mounting Style
SMD/SMT
封装 / 箱体
Package / Case
VSSOP-8
系列
Packaging
Cut Tape
系列
Packaging
Reel
工厂包装数量
Factory Pack Quantity
3000

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74LVC2G00-Q100
Dual 2-input NAND gate
Rev. 2 — 13 December 2016
Product data sheet
1. General description
The 74LVC2G00-Q100 provides a 2-input NAND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)

 
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