74LV573
Octal D-type transparent latch; 3-state
Rev. 03 — 15 April 2009
Product data sheet
1. General description
The 74LV573 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC573 and 74HCT573.
The 74LV573 consists of eight D-type transparent latches, featuring separate D-type
inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable
(LE) input and an output enable (OE) input are common to all internal latches.
When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches
are transparent, that is, a latch output will change each time its corresponding D-input
changes. When LE is LOW, the latches store the information that was present at the
D-inputs one set-up time preceding the HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the eight latches are available at the outputs. When OE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the latches.
The 74LV573 is functionally identical to the 74LV373, but has a different pin arrangement.
2. Features
I
I
I
I
I
I
I
I
I
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
°C
Inputs and outputs on opposite sides of package allowing easy interface with
microprocessors
Useful as input or output port for microprocessors
Common 3-state output enable input
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
I
I
NXP Semiconductors
74LV573
Octal D-type transparent latch; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV573N
74LV573D
74LV573DB
74LV573PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP20
SO20
SSOP20
TSSOP20
Description
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT146-1
SOT163-1
SOT339-1
SOT360-1
Type number
4. Functional diagram
11
1
1
2
3
4
5
6
7
8
9
OE
D0
D1
D2
D3
D4
D5
D6
D7
LE
11
mna807
C1
EN1
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
8
9
3
4
5
6
7
1D
19
18
17
16
15
14
13
12
mna808
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
2 of 18
NXP Semiconductors
74LV573
Octal D-type transparent latch; 3-state
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
LATCH
1 to 8
3-STATE
OUTPUTS
Q0 19
Q1 18
Q2 17
Q3 16
Q4 15
Q5 14
Q6 13
Q7 12
11 LE
1 OE
mna809
Fig 3.
Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LE LE
LATCH
2
LE LE
LATCH
3
LE LE
LATCH
4
LE LE
LATCH
5
LE LE
LATCH
6
LE LE
LATCH
7
LE LE
LATCH
8
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna810
Fig 4.
Logic diagram
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
3 of 18
NXP Semiconductors
74LV573
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
74LV573
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
001aaj966
74LV573
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
001aaj967
GND 10
GND 10
Fig 5.
Pin configuration DIP20, SO20
Fig 6.
Pin configuration SSOP20, TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
D0 to D7
GND
LE
Q0 to Q7
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
Description
output enable input (active LOW)
data input
ground (0 V)
latch enable input (active HIGH)
data output
supply voltage
6. Functional description
Table 3.
Functional table
[1]
Input
OE
Enable and read register
(transparent mode)
Latch and read register
Latch register and disable outputs
L
L
L
L
H
H
[1]
Operating modes
Internal latch Output
LE
H
H
L
L
L
L
Dn
L
H
l
h
l
h
L
H
L
H
L
H
Qn
L
H
L
H
Z
Z
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
4 of 18
NXP Semiconductors
74LV573
Octal D-type transparent latch; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
−40 °C
to +125
°C
DIP20
SO20, SSOP20 and TSSOP20
[1]
[2]
[2]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
−0.5
-
-
-
-
−70
−65
-
-
Max
+7.0
20
50
35
70
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP20 packages: above 70
°C
the value of P
tot
derates linearly with 12 mW/K.
For SO20 packages: above 70
°C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60
°C
the value of P
tot
derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Parameter
supply voltage
[1]
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
Min
1.0
0
0
−40
-
-
-
-
Typ
3.3
-
-
+25
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
74LV573_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 15 April 2009
5 of 18
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