19-3315; Rev 0; 7/04
KIT
ATION
EVALU
BLE
AVAILA
Programmable Audio Clock Generator
General Description
Features
♦
27MHz Crystal with
±30ppm
Frequency Reference
♦
Two Buffered Output Ports with Multiple Audio
Clocks: 256, 384, or 768 Times f
S
♦
Supports Standard and Double Sampling Rates
(12kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2 kHz,
and 96kHz)
♦
I
2
C Interface or Hardwired Output Clock Selection
♦
Separate Output Clock Enable
♦
Low Jitter Typical 21ps (RMS at 73.728MHz)
♦
No External Components for PLL
♦
Integrated VCXO with ±200ppm Tuning Range
♦
Small Footprint, Thin QFN Package, 4mm x 4mm
MAX9485
The MAX9485 programmable multiple-output clock
generator provides a cost-efficient solution for MPEG-2
audio systems such as DVD players, DVD drives for
multimedia PCs, digital HDTV systems, home entertain-
ment centers, and set-top boxes.
The MAX9485 accepts an input reference frequency of
27MHz from a crystal or system reference clock. The
device provides two buffered clock outputs of 256, 384,
or 768 times the chosen sampling frequency (f
S
) select-
ed through an I
2
C interface or hardwired inputs.
Sampling frequencies of 12kHz, 32kHz, 44.1kHz,
48kHz, 64kHz, 88.2kHz, or 96kHz are available. The
MAX9485 also offers a buffered 27MHz output and an
integrated voltage-controlled oscillator (VCXO) that is
tuned by a DC voltage generated from the MPEG
processor. The use of VCXO allows the audio system
clock to lock with the overall system clock.
The MAX9485 features the lowest jitter in its class, guar-
anteeing excellent dynamic performance with audio
ADCs and DACs in an MPEG-2 audio system. The
device operates with a 3.3V supply and is specified over
the -40°C to +85°C extended temperature range. The
MAX9485 is offered in 6.5mm x 4.4mm 20-pin TSSOP
and 4mm x 4mm 20-pin thin QFN packages.
Ordering Information
PART
MAX9485ETP
MAX9485EUP
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 Thin QFN-EP*
20 TSSOP
*EP
= Exposed pad.
Applications
Digital TVs
Set-Top Boxes
Home Entertainment
Centers
DVD Players
HDTVs
Pin Configurations
GND_P
V
DD_P
SAO2
MCLK
SAO1
TOP VIEW
V
DD_P
1
GND_P 2
TUN 3
X1 4
X2 5
V
DD
6
SCL/FS0 7
SDA/FS1 8
FS2 9
GND 10
20 SAO2
19 SAO1
18 MCLK
17 V
DD
TUN
X1
X2
V
DD
SCL/FS0
19
1
2
3
4
5
10
7
6
8
9
20
18
17
16
15
14
V
DD
CLK_OUT2
GND
CLK_OUT1
MODE
MAX9485
16 CLK_OUT2
15 GND
14 CLK_OUT1
13 MODE
MAX9485
EXPOSED PAD
(GROUND)
13
12
11
GND
12 RST
SDA/FS1
FS2
11 GND
TSSOP
THIN QFN
________________________________________________________________
Maxim Integrated Products
GND
RST
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
Programmable Audio Clock Generator
MAX9485
ABSOLUTE MAXIMUM RATINGS
V
DD,
V
DD_P
to GND ...............................................-0.3V to +4.0V
GND_P to GND ...................................................................±0.3V
All Inputs and Outputs to GND...................-0.3V to (V
DD
+ 0.3V)
Short-Circuit Duration of Outputs to GND ..................Continuous
Continuous Power Dissipation (T
A
= +70°C)
20-Pin TSSOP (derate 11mW/°C above +70°C) ......... 879mW
20-Lead Thin QFN (derate 16.9mW/°C
above +70°C).............................................................1349mW
Storage Temperature Range .............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
ESD Protection
Human Body Model (R
D
= 1.5kΩ, C
S
= 100pF)...........> ±2kV
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
DD
= V
DD_P
= 3.0V to 3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C, V
DD
= V
DD
_
P
= 3.3V.)
(Note 1)
PARAMETER
High Level-Input Voltage
Low Level-Input Voltage
Input Current
High Level-Input Voltage
Low Level-Input Voltage
Input Open Level
Input Current
Output High Level
Output Low Level
Input High Level
Input Low Level
Input Current
Low-Level Output
Input Capacitance
POWER SUPPLY (V
DD
, V
DD_P
)
Power-Supply Ranges
Power-Supply Current
V
DD,
V
DD_P
I
DD
+I
DD_P
CLK_OUT1, CLK_OUT2 at 73.728MHz,
no load, V
TUN
= 3.0V
3.0
3.3
12
3.6
V
mA
SYMBOL
V
IH1
V
IL1
I
IL1
V
IH2
V
IL2
V
IO2
I
IN
V
OH1
V
OL1
V
IH3
V
IL3
I
IN
V
OL3
C
IN
Input voltage = 0 or V
DD
I
OL3
= 4mA
8.4
Input open
Input voltage = 0 or V
DD
I
OH1
= -4mA
I
OL1
= 4mA
0.7 x V
DD
0
-1
Input voltage = 0 or V
DD
CONDITIONS
MIN
2.0
0.0
-20
2.5
0.0
1.3
-10
V
DD
- 0.6
0.4
V
DD
0.3 x V
DD
+1
0.4
TYP
MAX
V
DD
0.8
+20
V
DD
0.8
2.0
+10
UNITS
V
V
µA
V
V
V
µA
V
V
V
V
µA
V
pF
LVCMOS/LVTTL INPUTS (MODE,
RST,
X1)
(Note 2)
THREE-LEVEL INPUTS (FS0, FS1, FS2, SAO1, SAO2)
LVCMOS/LVTTL OUTPUTS (CLK_OUT1, CLK_OUT2, MCLK)
I
2
C INTERFACE INPUT AND OUTPUT (SCL, SDA)
2
_______________________________________________________________________________________
Programmable Audio Clock Generator
AC ELECTRICAL CHARACTERISTICS
(V
DD
= V
DD_P
= 3.0V to 3.6V, T
A
= -40°C to +85°C, output frequency is 73.728MHz, C
L
= 20pF, unless otherwise noted. Typical values
are at T
A
= +25°C, V
DD
= V
DD
_
P
= 3.3V.) (Note 3)
PARAMETER
VCXO (MCLK)
Crystal Frequency
Crystal Accuracy
Tuning Voltage Range
VCXO Tuning Range
TUN Input Impedance
Output Clock Frequency
Output Clock Accuracy
Output Duty Cycle
Output Jitter
Output Rise Time
Output Fall Time
Tuning Response Time
Power-On Settling Time
t
MJ
t
MR
t
MF
t
TUN
T
PO1
RMS
Figure 8
Figure 8
Figure 9
Figure 9
256 x f
S
Frequency Range (Note 5)
Clock Rise Time
Clock Fall Time
Duty Cycle
Output Clock Period Jitter
Frequency Settling Time
Power-On Time
t
RJ
t
FST
T
PO2
RMS
Figure 1
Figure 9
CLK_OUT1, 2 at 73.728MHz
(Note 6)
CLK_OUT1, 2 at 36.864MHz
f
out
t
R1
t
F1
384 x f
S
768 x f
S
Figure 8
Figure 8
45
8.192
12.288
24.576
2
2
50
21
37
10
15
ms
ms
55
R
TUN
f
MCLK
V
TUN
= 1.75V
V
TUN
= 1.75V (Note 4)
45
V
TUN
V
TUN
= 0 to 3.0V
0
-200
94
27
±50
55
28
2
2
10
5
24.576
36.864
73.728
ns
ns
%
ps
MHz
65
f
XTL
Nominal frequency
27
±30
3.0V
+200
MHz
ppm
V
ppm
kΩ
MHz
ppm
%
ps
ns
ns
µs
ms
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX9485
CLOCK OUTPUTS (CLK_OUT1, CLK_OUT2)
_______________________________________________________________________________________
3
Programmable Audio Clock Generator
MAX9485
I
2
C TIMING CHARACTERISTICS
(V
DD
= V
DD_P
= 3.0V to 3.6V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C, V
DD
= V
DD
_
P
= 3.3V;
Figure 7.) (Note 1)
PARAMETER
Serial Clock
Bus Free Time Between a STOP and
a START Condition
Hold Time (Repeated) START
Condition
Repeated START Condition Setup
Time
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of SDA and SCL, Receiving
Fall Time of SDA and SCL, Receiving
Fall Time of SDA, Transmitting
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus Line
SYMBOL
f
SCL
t
BUF
t
HD, STA
t
SU, STA
t
SU, STO
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
t
R
t
F
t
F
t
SP
C
b
(Notes 3, 8)
(Notes 3, 8)
(Notes 8, 9)
(Notes 3, 10)
(Note 7)
1.3
0.6
0.6
0.6
0.05
100
1.3
0.6
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
0
300
300
250
50
400
0.9
CONDITIONS
MIN
TYP
MAX
400
UNITS
kHz
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
ns
pF
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
All parameters tested at T
A
= +25°C. Specifications over temperature are guaranteed by design and characterization.
When X1 is used as an external reference.
Guaranteed by design and characterization; limits are set at ±6 sigma.
Includes crystal accuracy.
F
XTL
= 27MHz. Nominal frequency.
See frequency selection paragraph in the
Applications Information
section.
A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 8:
C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
Note 9:
Bus sink current is less than 6mA. C
b
= total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and
0.7 V
DD
.
Note 10:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
_______________________________________________________________________________________
Programmable Audio Clock Generator
MAX9485
Typical Operating Characteristics
(V
DD
= V
DD_P
= 3.3V, T
A
= +25°C.)
SUPPLY CURRENT
vs. LOAD CAPACITANCE
MAX9485 toc01
SUPPLY CURRENT vs. V
TUN
MAX9485 toc02
SUPPLY CURRENT
vs. OUTPUT FREQUENCY
V
TUN
= 1.5V
C
L
= 20pF
40
SUPPLY CURRENT (mA)
MAX9485 toc03
50
V
TUN
= 1.5V
f
CLK_OUT
= 73.728MHz
40
SUPPLY CURRENT (mA)
50
C
L
= 20pF
f
CLK_OUT
= 73.728MHz
40
SUPPLY CURRENT (mA)
50
30
30
30
20
20
20
10
10
10
0
0
10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
0
0
0.5
1.0
1.5
V
TUN
(V)
2.0
2.5
3.0
0
0
10
20
30
40
50
60
70
80
OUTPUT FREQUENCY (MHz)
OUTPUT CLOCK RISE/FALL TIME
vs. LOAD CAPACITANCE
MAX9485 toc04
MCLK PULLING RANGE
vs. V
TUN
C
X1
= C
X2
= 4.7pF
200
PULLING RANGE (ppm)
100
0
-100
-200
-300
C
X1
= C
X2
= 6.8pF
C
X1
= C
X2
= 5.6pF
MAX9485 toc05
3.0
2.5
RISE/FALL TIME (ns)
2.0
1.5
1.0
0.5
0
0
4
8
12
16
RISE TIME (t
R
)
FALL TIME (t
F
)
V
TUN
= 1.5V
f
CLK_OUT
= 73.728MHz
300
20
0
0.5
1.0
1.5
V
TUN
(V)
2.0
2.5
3.0
LOAD CAPACITANCE (pF)
MCLK PERIOD JITTER
vs. OUTPUT FREQUENCY
MAX9485 toc06
CLK_OUT PERIOD JITTER
vs. OUTPUT FREQUENCY
V
TUN
= 1.5V
C
L
= 15pF
400
PERIOD JITTER (ps
RMS
)
MAX9485 toc07
50
V
TUN
= 1.5V
C
L
= 15pF
40
PERIOD JITTER (ps
RMS
)
500
30
300
20
200
10
100
0
0
10
20
30
40
50
60
70
80
OUTPUT FREQUENCY (MHz)
0
0
10
20
30
40
50
60
70
80
OUTPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
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