without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
10/27/2016
1
IS61/64WV102416DALL
IS61/64WV102416DBLL
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
1
2
3
4
5
6
48-Pin TSOP ,TYPE I ( 12mm x 20mm )
A4
1
2
3
4
48
47
A5
A6
A7
A8
OE#
UB#
LB#
I/O15
I/O14
A
LB#
OE#
A0
A1
A2
NC
A3
A2
A1
A0
NC
46
45
44
43
42
5
6
7
8
B
I/O8
UB#
A3
A4
CE#
I/O0
CS#
I/O0
I/O1
I/O2
41
40
39
38
37
36
35
9
10
11
12
13
14
15
C
I/O9
I/O10
A5
A6
I/O1
I/O2
I/O3
VDD
VSS
I/O4
I/O13
I/O12
VSS
VDD
I/O11
I/O10
D
VSS
I/O11
A17
A7
I/O3
VDD
I/O5
I/O6
I/O7
34
33
32
31
16
17
18
19
20
I/O9
I/O8
NC
A9
A10
A11
E
VDD
I/O12
NC
A16
I/O4
VSS
WE#
NC
A19
30
29
28
27
26
F
I/O14
I/O13
A14
A15
I/O5
I/O6
A18
A17
A16
A15
21
22
23
24
A12
A13
25
A14
G
I/O15
A19
A12
A13
WE#
I/O7
H
A18
A8
A9
A10
A11
NC
PIN DESCRIPTIONS
A0-A19
I/O0-I/O15
CS#
OE#
WE#
LB#
UB#
NC
V
DD
VSS
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control
(I/O0-I/O7)
Upper-byte Control
(I/O8-I/O15)
No Connection
Power
Ground
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
10/27/2016
2
IS61/64WV102416DALL
IS61/64WV102416DBLL
FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM
has three different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS# HIGH). The input and output pins (I/O0-15) are placed in a high
impedance state. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS#) and Write Enable (WE#) input LOW. The input and output pins (I/O0-
15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB# and LB# enables a
byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the location specified
on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written into the location.
READ MODE
Read operation issues with Chip selected (CS# LOW) and Write Enable (WE#) input HIGH. When OE# is LOW, output
buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB# and LB# enables a
byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB# being LOW, data from
memory appears on I/O8-15.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
POWER UP INITIALIZATION
The device includes on-chip voltage sensor used to launch POWER-UP initialization process.
When VDD reaches stable level, the device requires 150us of tPU (Power-Up Time) to complete its self-initialization
process.
When initialization is complete, the device is ready for normal operation.
tPU
Stable VDD
150 us
VDD
0V
Device Initialization
Device for Normal Operation
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
CS#
H
L
L
L
L
L
L
L
L
WE#
X
H
H
H
H
H
L
L
L
OE#
X
H
H
L
L
L
X
X
X
LB#
X
L
H
L
H
L
L
H
L
UB#
X
L
L
H
L
L
H
L
L
I/O0-I/O7
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
I/O8-I/O15
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
VDD Current
ISB1, ISB2
ICC
ICC
Write
ICC
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
10/27/2016
3
IS61/64WV102416DALL
IS61/64WV102416DBLL
ABSOLUTE MAXIMUM RATINGS AND Operating Range
ABSOLUTE MAXIMUM RATINGS
Symbol
Vt er m
V
DD
tStg
P
T
Notes:
1.
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(1)
Parameter
Terminal Voltage with Respect to VSS
V
DD
Related to VSS
Storage Temperature
Power Dissipation
Value
–0.5 to V
DD
+ 0.5V
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
C
W
PIN CAPACITANCE
(1)
Parameter
Input capacitance
DQ capacitance (IO0–IO15)
Symbol
C
IN
C
I/O
Test Condition
T
A
= 25°C, f = 1 MHz, V
DD
= V
DD
(typ)
Max
6
8
Units
pF
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
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