SINGLE CHANNEL T1/E1/J1
SHORT HAUL LINE INTER-
FACE UNIT
FEATURES
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Single channel T1/E1/J1 short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
Single 3.3 V power supply with 5 V tolerance on digital interfaces
Meets or exceeds specifications in
-
ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
- AT&T Pub 62411
Software programmable or hardware selectable on:
- Wave-shaping templates
- Line terminating impedance (T1:100
Ω,
J1:110
Ω,
E1:75
Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
IDT82V2041E
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- PRBS (Pseudo Random Bit Sequence) generation and detection
with 2
15
-1 PRBS polynomials for E1
- QRSS (Quasi Random Sequence Signals) generation and detection
with 2
20
-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Adaptive receive sensitivity up to -20 dB (Host Mode only)
Short circuit protection and internal protection diode for line
drivers
LOS (Loss Of Signal) detection with programmable LOS levels
(Host Mode only)
AIS (Alarm Indication Signal) detection
Supports serial control interface, Motorola and Intel Multiplexed
interfaces and hardware control mode
Pin compatibe to 82V2081 T1/E1/J1 Long Haul/Short Haul LIU
and 82V2051E E1 Short Haul LIU
Package:
Available in 44-pin TQFP packages
Green package options available
DESCRIPTION
The IDT82V2041E can be configured as a single channel T1, E1 or J1
Line Interface Unit. The IDT82V2041E performs clock/data recovery, AMI/
B8ZS/HDB3 line decoding and detects and reports the LOS conditions. An
integrated Adaptive Equalizer is available to increase the receive sensitivity
and enable programming of LOS levels. In transmit path, there is an AMI/
B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter Attenua-
tor, which can be placed in either the receive path or the transmit path. The
Jitter Attenuator can also be disabled. The IDT82V2041E supports both
Single Rail and Dual Rail system interfaces. To facilitate the network main-
tenance, a PRBS/QRSS generation/detection circuit is integrated in the
chip, and different types of loopbacks can be set according to the applica-
tions. Four different kinds of line terminating impedance, 75
Ω,
100
Ω,
110
Ω
and 120
Ω
are selectable. The chip also provides driver short-circuit pro-
tection and internal protection diode. The chip can be controlled by either
software or hardware.
The IDT82V2041E can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
2005 Integrated Device Technology, Inc.
December 9, 2005
DSC-6775/1
IDT82V2041E
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL BLOCK DIAGRAM
LOS
RCLK
RD/RDP
CV/RDN
LOS/AIS
Detector
B8ZS/
HDB3/AMI
Decoder
PRBS Detector
IBLC Detector
Data and
Clock
Recovery
Data
Slicer
Adaptive
Equalizer
Receiver
Internal
Termination
Analog
Loopback
Transmitter
Internal
Termination
TTIP
TRING
RTIP
RRING
Jitter
Attenuator
Remote
Loopback
Digital
Loopback
Waveform
Shaper
Line
Driver
TCLK
TD/TDP
TDN
B8ZS/
HDB3/AMI
Decoder
PRBS Generator
IBLC Generator
TAOS
Clock
Generator
Jitter
Attenuator
Software Control Interface
Register
Files
Pin Control
SDI/
WR
/R/W
SDO /
ACK
/
RDY
RD
/
DS
/ SCLKE
SCLK/ALE/AS
Figure-1 Block Diagram
Functional Block Diagram
2
MODE[1:0]
TERM
RXTXM[1:0]
PULS[3:0]
PATT[1:0]
JA[1:0]
MONT
LP[1:0]
THZ
RCLKE
RPD
RST
VDDIO
VDDD
VDDA
VDDT
MCLK
AD[7:0]
INT
CS
December 9, 2005
Table of Contents
1
2
3
IDT82V2041E Pin Configurations ............................................................................................... 8
Pin Description ............................................................................................................................ 9
Functional Description .............................................................................................................. 15
3.1
Control Mode Selection .................................................................................................... 15
3.2
T1/E1/J1 Mode Selection .................................................................................................. 15
3.3
Transmit Path ................................................................................................................... 15
3.3.1 Transmit Path System Interface.............................................................................. 15
3.3.2 Encoder.................................................................................................................. 15
3.3.3 Pulse Shaper .......................................................................................................... 15
3.3.3.1 Preset Pulse Templates .......................................................................... 15
3.3.3.2 User-Programmable Arbitrary Waveform ................................................ 17
3.3.4 Transmit Path Line Interface................................................................................... 20
3.3.5 Transmit Path Power Down .................................................................................... 20
3.4
Receive Path .................................................................................................................... 21
3.4.1 Receive Internal Termination .................................................................................. 21
3.4.2 Line Monitor ............................................................................................................ 22
3.4.3 Adaptive Equalizer .................................................................................................. 23
3.4.4 Receive Sensitivity.................................................................................................. 23
3.4.5 Data Slicer .............................................................................................................. 23
3.4.6 CDR (Clock & Data Recovery)................................................................................ 23
3.4.7 Decoder .................................................................................................................. 23
3.4.8 Receive Path System Interface............................................................................... 24
3.4.9 Receive Path Power Down ..................................................................................... 24
3.5
Jitter Attenuator ................................................................................................................ 24
3.5.1 Jitter Attenuation Function Descripton .................................................................... 24
3.5.2 Jitter Attenuator Performance ................................................................................. 25
3.6
Los And AIS Detection ...................................................................................................... 25
3.6.1 LOS Detection......................................................................................................... 25
3.6.2 AIS Detection .......................................................................................................... 26
3.7
Transmit And Detect Internal Patterns .............................................................................. 28
3.7.1 Transmit All Ones ................................................................................................... 28
3.7.2 Transmit All Zeros................................................................................................... 28
3.7.3 PRBS/QRSS Generation And Detection................................................................. 28
3.8
Loopback .......................................................................................................................... 28
3.8.1 Analog Loopback .................................................................................................... 28
3.8.2 Digital Loopback ..................................................................................................... 28
3.8.3 Remote Loopback................................................................................................... 28
Table of Contents
3
December 9, 2005
IDT82V2041E
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
4
3.8.4 Inband Loopback .................................................................................................... 30
3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 30
3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 30
3.8.4.3 Automatic Remote Loopback .................................................................. 31
Error Detection/Counting And Insertion ............................................................................ 32
3.9.1 Definition Of Line Coding Error ............................................................................... 32
3.9.2 Error Detection And Counting ................................................................................. 32
3.9.3 Bipolar Violation And PRBS Error Insertion ............................................................ 33
Line Driver Failure Monitoring ........................................................................................... 33
MCLK And TCLK .............................................................................................................. 34
3.11.1 Master Clock (MCLK).............................................................................................. 34
3.11.2 Transmit Clock (TCLK) ........................................................................................... 34
Microcontroller Interfaces ................................................................................................. 35
3.12.1 Parallel Microcontroller Interface ............................................................................ 35
3.12.2 Serial Microcontroller Interface ............................................................................... 35
Interrupt Handling ............................................................................................................. 35
5V Tolerant I/O Pins ......................................................................................................... 36
Reset Operation ................................................................................................................ 36
Power Supply .................................................................................................................... 36
Programming Information ........................................................................................................ 37
4.1
Register List And Map ...................................................................................................... 37
4.2
Reserved Registers .......................................................................................................... 37
4.3
Register Description ......................................................................................................... 38
4.3.1 Control Registers .................................................................................................... 38
4.3.2 Transmit Path Control Registers............................................................................. 40
4.3.3 Receive Path Control Registers.............................................................................. 42
4.3.4 Network Diagnostics Control Registers .................................................................. 44
4.3.5 Interrupt Control Registers...................................................................................... 47
4.3.6 Line Status Registers.............................................................................................. 50
4.3.7 Interrupt Status Registers ....................................................................................... 52
4.3.8 Counter Registers ................................................................................................... 54
Hardware Control Pin Summary .............................................................................................. 55
Test Specifications .................................................................................................................... 57
Microcontroller Interface Timing Characteristics ................................................................... 70
7.1
Serial Interface Timing ...................................................................................................... 70
7.2
Parallel Interface Timing ................................................................................................... 71
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6
7
Table of Contents
4
December 9, 2005
List of Tables
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Table-41
List of Tables
Pin Description ................................................................................................................ 9
Transmit Waveform Value For E1 75 ohm.................................................................... 17
Transmit Waveform Value For E1 120 ohm.................................................................. 18
Transmit Waveform Value For T1 0~133 ft................................................................... 18
Transmit Waveform Value For T1 133~266 ft............................................................... 18
Transmit Waveform Value For T1 266~399 ft............................................................... 18
Transmit Waveform Value For T1 399~533 ft............................................................... 19
Transmit Waveform Value For T1 533~655 ft............................................................... 19
Transmit Waveform Value For J1 0~655 ft ................................................................... 19
Impedance Matching for Transmitter ............................................................................ 20
Impedance Matching for Receiver ................................................................................ 21
Criteria of Starting Speed Adjustment........................................................................... 25
LOS Declare and Clear ................................................................................................ 26
LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 26
AIS Condition ................................................................................................................ 27
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 28
EXZ Definition ............................................................................................................... 32
Interrupt Event............................................................................................................... 36
Register List and Map ................................................................................................... 37
ID: Device Revision Register ........................................................................................ 38
RST: Reset Register ..................................................................................................... 38
GCF: Global Configuration Register ............................................................................. 38
TERM: Transmit and Receive Termination Configuration Register .............................. 38
JACF: Jitter Attenuation Configuration Register ........................................................... 39
TCF0: Transmitter Configuration Register 0 ................................................................. 40
TCF1: Transmitter Configuration Register 1 ................................................................. 40
TCF2: Transmitter Configuration Register 2 ................................................................. 41
TCF3: Transmitter Configuration Register 3 ................................................................. 41
TCF4: Transmitter Configuration Register 4 ................................................................. 41
RCF0: Receiver Configuration Register 0..................................................................... 42
RCF1: Receiver Configuration Register 1..................................................................... 42
RCF2: Receiver Configuration Register 2..................................................................... 43
MAINT0: Maintenance Function Control Register 0...................................................... 44
MAINT1: Maintenance Function Control Register 1...................................................... 44
MAINT2: Maintenance Function Control Register 2...................................................... 45
MAINT3: Maintenance Function Control Register 3...................................................... 45
MAINT4: Maintenance Function Control Register 4...................................................... 45
MAINT5: Maintenance Function Control Register 5...................................................... 45
MAINT6: Maintenance Function Control Register 6...................................................... 46
INTM0: Interrupt Mask Register 0 ................................................................................. 47
INTM1: Interrupt Masked Register 1 ............................................................................. 48
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December 9, 2005
FPGA/CPLD
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