NS9360 Datasheet
The Digi NS9360 is a single chip 0.13μm CMOS network-attached processor. The CPU is the
ARM926EJ-S core with MMU, DSP extensions, Jazelle Java accelerator, and 8 kB of instruction cache
and 4 kB of data cache in a Harvard architecture. The NS9360 runs up to 177 MHz, with a 88 MHz
system and memory bus and 44 MHz peripheral bus. The NS9360 operates at a 1.5V core and
3.3V I/O ring voltages.
With its extensive set of I/O
NS9360
interfaces, Ethernet high-speed
272 - pin BGA, lead-free, RoHS compliant
performance and processing
capacity, the NS9360 is the most
USB Host
JTAG Test
and Debug
ARM
capable highly-integrated 32-bit
ARM926EJ-S
103 to 177 MHz
USB Device
network-attached processor
Real
8kB I-Cache
Time
4K
4kB D-Cache
Clock
available. The NS9360 is designed
1284
specifically for use in high-
10/100
Distributed
Ethernet
Serial
Module
MII/RMII
performance intelligent
DMA
x4
MAC
networked devices and Internet
UART
50 to 90 MHz AMBA AHB Bus
Memory
32b-D, 32b-A
appliances including high-
Controller
SPI
performance/low-latency remote
Ext.
Peripheral
Controller
I/O, intelligent networked
CLK Generation
I C
information displays, and
Vectored Interrupt
Controller
LCD Controller
streaming and surveillance
Power Manager
8 x Timers/Counters
cameras. The NS9360 is a member
AHB Arbiter
or 4 PWM
of the award-winning NET+ARM
family of system-on-chip (SOC) solutions for embedded systems.
25 to 45 MHz Peripheral Bus
27-Channel DMA
32b-D, 32b-A
GPIO (50 Pins)
2
7 GPIO
16 GPIO
The NS9360 offers a connection to an external bus expansion module as well as a glueless
connection to SDRAM, PC100 DIMM, Flash, EEPROM, and SRAM memories. It includes a versatile
embedded LCD controller supporting up to 64K color TFT or 3375 color STN LCD display. The NS9360
features a USB port for applications requiring WLAN, external storage, or external sensors, imagers,
or scanners. Four multi-function serial ports, an I
2
C port, and 1284 parallel port provide a standard
glueless interface to a variety of external peripherals. The NS9360 features up to 73 general
purpose I/O (GPIO) pins and highly-configurable power management with sleep mode.
NET+ARM processors are the foundation for the NET+Works® family of integrated hardware and
software solutions for device networking. These comprehensive platforms include drivers,
operating systems, networking software, development tools, APIs, and complete development
boards.
Using the NS9360 and associated Net+Works packages allows system designers to achieve dramatic
time-to-market reductions with pre-integrated and tested NET+ARM hardware, NET+Works
software, and tools. Product unit costs are reduced dramatically with complete system-on-chip,
including Ethernet, display support, a robust peripheral set, and the processing headroom to meet
the most demanding applications. Customers save engineering resources, as no network
development is required. Companies will reduce their design risk with a fully integrated and tested
solution.
A complete NET+Works development package includes ThreadX™ picokernel RTOS, Green Hills™
MULTI® 2000 IDE or Microcross GNU X-Tools™, drivers, networking protocols and services with APIs,
NET+ARM-based development board, Digi-supplied utilities, Integrated File System, JTAG In Circuit
Emulator (ICE), and support for Boundary Scan Description Language (BSDL). One year software
maintenance and technical support is available.
Contents
NS9360 Features ........................................................................... 1
System-level interfaces ................................................................... 4
System configuration ...................................................................... 5
System boot................................................................................. 8
Reset......................................................................................... 9
RESET_DONE as an input ........................................................ 9
SPI boot sequence ................................................................ 9
RESET_DONE as an output....................................................... 9
System Clock .............................................................................. 10
USB clock................................................................................... 13
NS9360 pinout and signal descriptions ................................................ 14
System Memory interface ...................................................... 14
System Memory interface signals ............................................. 17
Ethernet interface............................................................... 19
Clock generation/system pins ................................................. 20
bist_en_n, pll_test_n, and scan_en_n........................................ 21
GPIO MUX ......................................................................... 21
LCD module signals.............................................................. 31
I2C interface ..................................................................... 34
USB Interface..................................................................... 34
JTAG interface for ARM core/boundary scan ............................... 35
Reserved pins .................................................................... 36
Power and ground ............................................................... 36
Address and register maps .............................................................. 37
System address map ............................................................ 37
BBus peripheral address map .................................................. 38
Electrical characteristics ................................................................ 39
Absolute maximum ratings..................................................... 39
Recommended operating conditions ......................................... 39
Power dissipation................................................................ 40
DC electrical characteristics ............................................................ 41
Inputs.............................................................................. 41
Outputs............................................................................ 42
Reset and edge sensitive input timing requirements ............................... 43
Power sequencing......................................................................... 44
Memory timing ............................................................................ 45
SDRAM timing diagrams......................................................... 45
SRAM timing diagrams .......................................................... 50
Slow peripheral acknowledge timing ......................................... 57
Ethernet timing ........................................................................... 59
I2C timing .................................................................................. 61
LCD timing ................................................................................. 62
SPI timing .................................................................................. 66
1
IEEE 1284 timing .......................................................................... 69
USB internal PHY timing ................................................................. 70
USB external PHY interface ............................................................. 72
Reset and hardware strapping timing ................................................. 73
JTAG timing................................................................................ 74
Clock timing ............................................................................... 75
Packaging .................................................................................. 77
Product specifications .......................................................... 80
2
NS9360 Datasheet Rev. D
09/2007
NS9360 Features
NS9360 Features
32-bit ARM926EJ-S RISC processor
103 to 177 MHz
5-stage pipeline with interlocking
Harvard architecture
8 kB instruction cache and 4 kB data cache
32-bit ARM and 16-bit Thumb instruction
sets. Can be mixed for performance/code
density tradeoffs
MMU to support virtual memory-based OSs
such as Linux, WinCE/Pocket PC, VxWorks,
others
DSP instruction extensions, improved
divide, single cycle MAC
ARM Jazelle, 1200CM (coffee marks) Java
accelerator
EmbeddedICE-RT debug unit
JTAG boundary scan, BSDL support
External system bus interface
32-bit data, 32-bit internal address bus,
28-bit external address bus
Glueless interface to SDRAM, SRAM,
EEPROM, buffered DIMM, Flash
4 static and 4 dynamic memory chip
selects
1-32 wait states per chip select
A shared Static Extended Wait register
allows transfers to have up to 16368
wait states that can be externally
terminated.
Self-refresh during system sleep mode
Automatic dynamic bus sizing to 8 bits, 16
bits, 32 bits
Burst mode support with automatic data
width adjustment
Two external DMA channels for external
peripheral support
System Boot
High-speed boot from 8-bit, 16-bit, or
32-bit ROM or Flash
Hardware-supported low cost boot from
serial EEPROM through SPI port (patent
pending)
High performance 10/100 Ethernet MAC
10/100 Mbps MII/RMII PHY interfaces
Full-duplex or half-duplex
Station, broadcast, or multicast address
filtering
2 kB RX FIFO
256 byte TX FIFO with on-chip buffer
descriptor ring
–
Eliminates underruns and decreases
bus traffic
Separate TX and RX DMA channels
Intelligent receive-side buffer size
selection
Full statistics gathering support
External CAM filtering support
Flexible LCD controller
Supports most commercially available
displays:
–
–
–
18-bit active Matrix color TFT displays
Single and dual panel color STN
displays
Single and dual-panel monochrome
STN displays
Formats image data and generates timing
control signals
Internal programmable palette LUT and
grayscaler support different color
techniques
Programmable panel-clock frequency
www.digi.com
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