Integrated Device Technology, Inc.
ICS1526
Video Clock Synthesizer
General Description
The ICS1526 is a low-cost, high-performance
frequency generator. It is suited to general purpose
phase controlled clock synthesis as well as
line-locked and genlocked high-resolution video
applications. Using IDT’s advanced low-voltage
CMOS mixed-mode technology, the ICS1526 is an
effective clock synthesizer that supports video
projectors and displays at resolutions from VGA to
beyond XGA.
The ICS1526 offers single-ended clock outputs to 110
MHz. The HSYNC_out, and VSYNC_out pins provide
the regenerated versions of the HSYNC and VSYNC
inputs synchronous to the CLK output.
The advanced PLL uses its internal programmable
feedback divider. The device is programmed by a
standard I
2
C-bus™ serial interface and is available in
a TSSOP16 package.
Features
• Lead-free packaging (Pb-free)
• Low jitter (typical 27 ps short term jitter)
• Wide input frequency range
• 8 kHz to 100 MHz
• LVCMOS single-ended clock outputs
• Up to 110 MHz
• Uses 3.3 V power supply
• 5 Volt tolerant Inputs (HSYNC, VSYNC)
• Coast (ignore HSYNC) capability via VSYNC pin
• Industry standard I
2
C-bus programming interface
• PLL Lock detection via I
2
C or LOCK output pin
• 16-pin TSSOP package
Applications
• Frequency synthesis
• LCD monitors, video projectors and plasma displays
• Genlocking multiple video subsystems
ICS1526 Functional Diagram
OSC
HSYNC
VSYNC
I
2
C
HSYNC_out
Pin Configuration (16-pin TSSOP)
VSSD
SDA
SCL
VSYNC
HSYNC
VDDA
VSSA
OSC
ICS1526
VSYNC_out
CLK
LOCK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDD
VSSQ
VSYNC_out
VDDQ
CLK
HSYNC_out
LOCK
I2CADR
MDS 1526 P
IDT reserves the right to make changes in the preliminary device data
identified in this publication without notice. IDT advises its customers
to obtain the latest version of all device data to verify that information
being relied upon is current and accurate.
Revision 051310
ICS1526 Data Sheet
Section 1 Overview
Section 1
Overview
The ICS1526 has the ability to operate in line-locked
mode with the HSYNC input.
The ICS1526 is a user-programmable,
high-performance general purpose clock generator. It
is intended for graphics system line-locked and
genlocked applications and provides the clock signals
required by high-performance analog-to-digital
converters.
1.1 Phase-Locked Loop
The phase-locked loop has a very wide input frequency
range (8 kHz to 100 MHz). Not only is the ICS1526 an
excellent, general purpose clock synthesizer, but it is
also capable of line-locked operation. Refer to the
block diagram below.
Figure 1-1
Simplified Block Diagram
OSC
HSYNC
Divider
3..129
PFD
CP
VCO
VCOD
2,4,8,16
CLK
FD
12..4103
Flip-flop
VSYNC
Flip-flop
HSYNC_out
VSYNC_out
Note: Polarity controls and other circuit elements are not shown in above diagram for simplicity
The heart of the ICS1526 is a voltage controlled
oscillator (VCO). The VCOs speed is controlled by the
voltage on the loop filter. This voltage will be described
later in this section.
The VCOs clock output is first passed through the VCO
Divider (VCOD). The VCOD allows the VCO to operate
at higher speeds than the required output clock.
NOTE:
Under normal, locked operation the VCOD has
no effect on the speed of the output clocks, just the
VCO frequency.
The output of the VCOD is the full speed output
frequency seen on the CLK. This clock is then sent
through the 12-bit internal Feedback Divider (FD). The
feedback divider controls how many clocks are seen
during every cycle of the input reference.
The Phase Frequency Detector (PFD) then compares
the feedback to the input and controls the filter voltage
by enabling and disabling the charge pump. The
charge pump has programmable current drive and will
source and sink current as appropriate to keep the
input and the clock output aligned.
MDS 1526 P
2
The input HSYNC and VSYNC can be conditioned by a
high-performance Schmitt-trigger by sharpening the
rising/falling edge.
The HSYNC_out and VSYNC_out signals are aligned
with the output clock (CLK) via a set of flip flops.
1.2 Output Drivers and Logic Inputs
The ICS1526 uses low-voltage TTL (LVTTL) inputs and
LVCMOS outputs, operating at the 3.3 V supply
voltage. The LVTTL inputs are 5 V tolerant.
The LVCMOS drive resistive terminations or
transmission lines.
1.3 Automatic Power-On Reset Detection
The ICS1526 has automatic power-on reset detection
(POR) circuitry and it resets itself if the supply voltage
drops below threshold values. No external connection
to a reset signal is required.
Revision 051310
In te grated Devi ce Te ch nol ogy, Inc. ww w.idt. c o m Te c h Su p p o rt : w w w.idt.com/go/clockhelp
(
IDT™
/
ICS™
)
ICS1526 Data Sheet
Section 1 Overview
1.4 I
2
C Bus Serial Interface
The ICS1526 uses a 5 volt tolerant, industry-standard
I
2
C-bus serial interface that runs at either low speed
(100 kHz) or high speed (400 kHz). The interface uses
12 word addresses for control and status: one
write-only, eight read/write, and three read-only
addresses.
Two ICS1526 devices can sit on the same I
2
C bus,
each selected by the Master according to the state of
the I2CADR pin. The 7-bit device address is 0100110
(binary) when I2CADR is low. The device address is
0100111 (binary) when I2CADR is high. See
Section 4,
“Programming”
MDS1526 P
3
Revision 051310
In te grated Devi ce Te ch nol ogy, Inc. ww w.idt. c o m Te c h Su p p o rt : w w w.idt.com/go/clockhelp
(
IDT™
/
ICS™
)
ICS1526 Data Sheet
Section 2 Pin Descriptions
Section 2
Pin Descriptions
TYPE
POWER
IN/OUT
IN
IN
IN
POWER
POWER
IN
IN
LVCMOS
OUT
LVCMOS
OUT
LVCMOS
OUT
POWER
LVCMOS
OUT
POWER
POWER
DESCRIPTION
Digital ground
Serial data
Serial clock
Vertical sync
Horizontal sync
Analog supply
Analog ground
Oscillator
I
2
C device address
Lock
HSYNC output
Pixel clock output
Output driver supply
VSYNC output
Output driver ground
Digital supply
Clock input to PLL
Power for analog circuitry
Ground for analog circuitry
Input from crystal oscillator package
Chip I
2
C address select
PLL Lock detect
Schmitt-trigger filtered HSYNC
realigned with the output pixel clock
LVCMOS driver for full speed clock
Power for output drivers
Schmitt-trigger filtered VSYNC
realigned with the output pixel clock
Ground for output drivers
Power for digital sections
1&2
I
2
C-bus
I
2
C-bus
1
1
1&2
1&2
COMMENTS
Notes
Table 2-1
ICS1526
Pin Descriptions
PIN NO. PIN NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSSD
SDA
SCL
VSYNC
HSYNC
VDDA
VSSA
OSC
I2CADR
LOCK
HSYNC_out
CLK
VDDQ
VSYNC_out
VSSQ
VDDD
Notes: 1. These LVTTL inputs are 5 V tolerant.
2. Connect to ground if unused.
MDS 1526 P
4
Revision 051310
In te grated Devi ce Te ch nol ogy, Inc. ww w.idt. c o m Te c h Su p p o rt : w w w.idt.com/go/clockhelp
(
IDT™
/
ICS™
)
ICS1526 Data Sheet
Section 3 Register map summary
Section 3
Word
Address
00h
Register map summary
Reset
Value
1
0
Name
Input
Control
Access
R/W
Bit Name
CPen
VSYNC_Pol
Bit #
0
1
Description
Charge Pump Enable
0=External Enable via VSYNC, 1=Always Enabled
VSYNC Polarity (Charge Pump Enable)
Requires 00h:0=0
0=Coast (charge pump disabled) while VSYNC low,
1=Coast (charge pump disabled) while VSYNC high
HSYNC Polarity
0=Rising Edge, 1=Falling Edge
Reserved
Part requires a 0 for correct operation
Reserved
Enable PLL Lock Output
0=Disable, 1=Enable
Reserved
HSYNC_Pol
Reserved
Reserved
Reserved
EnPLS
Reserved
2
3
4
5
6
7
0
0
0
0
1
0
01h
Loop
Control
*
R/W
ICP0-2
0-2
ICP (Charge Pump Current)
Bit 2,1,0 = {000 =1
µA,
001 = 2
µA,
010 = 4
µA...
110 = 64
µA,
111 =
128
µA}.
Increasing the Charge Pump Current makes the loop
respond faster, raising the loop bandwidth. The typical value when
using the internal loop filter is 011.
Reserved
VCO Divider
Bit 5,4 = {00 = ÷2, 01=÷4, 10=÷8, 11=÷16}
Reserved
Reserved
VCOD0-1
Reserved
3
4-5
6-7
02h
FdBk Div
0
*
R/W
FBD0-7
0-7
Feedback Divider LSBs (bits 0-7)
03h
FdBk Div
1
*
R/W
FBD8-11
0-3
Feedback Divider MSBs (bits 8-11)
Divider setting = 12-bit word + 8
Minimum 12 = 000000000100
Maximum 4103 =111111111111
Reserved
Reserved
4-7
04h
Reserved
Reserved
0-7
0
Reserved
05h
Schmitt-
trigger
*
R/W
Schmitt
control
Metal_Rev
0
1-7
1
0
Schmitt-trigger control
0=Schmitt-trigger, 1=No Schmitt-trigger
Metal Mask Revision Number
06h
Output
Enables
R/W
Reserved
OE
Reserved
0
1
2-7
0
0
0
Reserved
Output Enable for CLK, HSYNC_out, VSYNC_out
0=High Impedance (disabled), 1=Enabled
Reserved
MDS1526 P
5
Revision 051310
In te grated Devi ce Te ch nol ogy, Inc. ww w.idt. c o m Te c h Su p p o rt : w w w.idt.com/go/clockhelp
(
IDT™
/
ICS™
)
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