Low Skew, 1-to-4 Differential-to-2.5V, 3.3V
LVPECL/ECL Fanout Buffer
General Description
The IDT8T33FS314I is a low skew 1-to-4 Differential Fanout Buffer,
designed with clock distribution in mind, accepting two clock sources
into an input MUX. The MUX is controlled by a CLK_SEL pin. This
makes the IDT8T33FS314I very versatile, in that, it can operate as
both a differential clock buffer as well as a signal-level translator and
fanout buffer.
The device is designed on a SiGe process and can operate at
frequencies in excess of 2.7GHz. This ensures negligible jitter
introduction to the timing budget which makes it an ideal choice for
distributing high frequency, high precision clocks across back planes
and boards in communication systems. Internal temperature
compensation guarantees consistent performance across various
platforms.
IDT8T33FS314I
DATA SHEET
Features
•
•
•
•
•
•
•
•
•
Four differential ECL/LVPECL level outputs
One differential ECL/LVPECL or single-ended input (CLKA)
One differential HSTL or single-ended input (CLKB)
Maximum output frequency: 2.7GHz
Additive phase jitter, RMS: 0.114ps (typical) @ 156.25MHz
Output skew: 50ps (maximum)
LVPECL and HSTL mode operating voltage supply range:
V
CC
= 2.5V±5% or 3.3V±5%, V
EE
= 0V
ECL mode operating voltage supply range:
V
EE
= -3.3V±5% or -2.5V±5%, V
CC
= 0V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
V
CC
CLKA
Pulldown
nCLKA
Pullup/Pulldown
0
V
CC
CLKB
Pulldown
nCLKB
Pullup/Pulldown
V
EE
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
V
EE
Pin Assignment
V
CC
nc
V
CC
CLK_SEL
CLKA
nCLKA
CLKB
nCLKB
V
EE
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
V
CC
IDT8T33FS314I
20-Lead 209-MIL SSOP
5.3mm x 7.2mm x 1.75mm body package
PY Package
Top View
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm body package
PG Package
Top View
CLK_SEL
Pulldown
V
EE
IDT8T33FS314PGI REVISION A MARCH 7, 2014
1
©2014 Integrated Device Technology, Inc.
IDT8T33FS314I Data Sheet
LOW SKEW, 1-to-4 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 3, 10
11, 20
2
4
5
6
7
8
9
12, 13
14, 15
16, 17
18, 19
Name
V
CC
nc
CLK_SEL
CLKA
nCLKA
CLKB
nCLKB
V
EE
nQ3,Q3
nQ2,Q2
nQ1,Q1
nQ0,Q0
Power
Unused
Input
Input
Input
Input
Input
Power
Output
Output
Output
Output
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Positive supply pins.
No connect.
Clock select input. When HIGH, selects CLKB, nCLKB inputs.
When LOW, selects CLKA, nCLKA inputs.
Default non-inverting differential clock input.
LVPECL/ECL interface levels.
Default inverting differential clock input. LVPECL/ECL interface levels.
Alternative non-inverting differential clock input. HSTL interface levels.
Alternative inverting differential clock input. HSTL interface levels.
Negative supply pin.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
CLK_SEL
Minimum
Typical
2
75
75
Maximum
Units
pF
k
k
IDT8T33FS314PGI REVISION A MARCH 7, 2014
2
©2014 Integrated Device Technology, Inc.
IDT8T33FS314I Data Sheet
LOW SKEW, 1-to-4 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Package Thermal Impedance,
JA
20-Lead SSOP
20-Lead TSSOP
Storage Temperature, T
STG
Rating
3.9V (LVPECL mode, V
EE
= 0V)
-3.9V (ECL mode, V
CC
= 0V)
-0.3V to V
CC
+ 0.3V
0.3V to V
EE
– 0.3V
50mA
100.4C/W (0 mps)
115.0C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. LVPECL DC Characteristics,
V
CC
= 2.5V ±5% or 3.3V ±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Control Input CLK_SEL
V
IL
V
IH
I
IN
Input Low Voltage
Input High Voltage
Input Current
V
IN
= V
IL
or V
IN
= V
IH
V
CC
- 1.810
V
CC
- 1.165
V
CC
- 1.475
V
CC
- 0.880
100
V
V
µA
Clock Input Pair CLKA, nCLKA (LVPECL Differential Signals)
V
PP
V
CMR
I
IN
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 2
Input Current
V
IN
= V
IL
or V
IN
= V
IH
0.1
1.0
1.3
V
CC
- 0.3
100
V
V
µA
Clock Input Pair CLKB, nCLKB (HSTL Differential Signals)
V
DIF
V
X
I
IN
Differential Input Voltage; NOTE 3
Differential Crosspoint Voltage; NOTE 4
Input Current
V
IN
= V
x
±0.2V
V
CC
= 3.3V
V
CC
= 2.5V
0.4
0.4
0
0.68 - 0.9
V
CC
- 1.0
200
V
V
V
µA
LVPECL Clock Outputs (Q[0:3], nQ[0:3])
V
OH
V
OL
Output High Voltage
Output Low Voltage
V
CC
= 3.3V ±5%
V
CC
= 2.5V ±5%
V
CC
- 1.2
V
CC
- 1.9
V
CC
- 1.9
V
CC
- 0.808
V
CC
- 1.689
V
CC
- 1.662
V
CC
- 0.7
V
CC
- 1.5
V
CC
- 1.3
V
V
V
Supply Current
I
EE
Maximum Quiescent Supply Current
without Output Termination Current
49
60
mA
NOTE 1: V
PP
is the minimum differential input voltage swing required to maintain device functionality.
NOTE 2: V
CMR
is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
specification.
NOTE 3: V
DIF
is the minimum differential HSTL input voltage swing required for device functionality.
NOTE 4: V
X
is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the V
X
range
and the input swing lies within the V
PP
specification.
IDT8T33FS314PGI REVISION A MARCH 7, 2014
3
©2014 Integrated Device Technology, Inc.
IDT8T33FS314I Data Sheet
LOW SKEW, 1-to-4 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Table 3B. ECL DC Characteristics,
V
CC
= 0V, V
EE
= -3.3V±5% or -2.5V±5%, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Control Input CLK_SEL
V
IL
V
IH
I
IN
Input Low Voltage
Input High Voltage
Input Current
V
IN
= V
IL
or V
IN
= V
IH
-1.810
-1.165
-1.475
-0.880
100
V
V
µA
Clock Input Pair CLKA, nCLKA (LVPECL Differential Signals)
V
PP
V
CMR
I
IN
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 2
Input Current
V
IN
= V
IL
or V
IN
= V
IH
0.1
V
EE
+ 1.0
1.3
-0.3
100
V
V
µA
LVPECL Clock Outputs (Q[0:3], nQ[0:3])
V
OH
V
OL
Output High Voltage
Output Low Voltage
V
EE
= -3.3V ±5%
V
EE
= -2.5V ±5%
-1.2
-1.9
-1.9
-0.808
-1.689
-1.662
-0.7
-1.5
-1.3
V
V
V
Supply Current
I
EE
Maximum Quiescent Supply Current
without Output Termination Current
49
60
mA
NOTE 1: V
PP
is the minimum differential input voltage swing required to maintain device functionality.
NOTE 2: V
CMR
is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
CMR
range
and the input swing lies within the V
PP
specification.
IDT8T33FS314PGI REVISION A MARCH 7, 2014
4
©2014 Integrated Device Technology, Inc.
IDT8T33FS314I Data Sheet
LOW SKEW, 1-to-4 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
AC Electrical Characteristics
Table 4. AC Characteristics,
(LVPECL/HSTL), V
CC
= 3.3V ±5% or 2.5V ±5%, V
EE
= 0V, or
(ECL) V
EE
= -3.3V ±5% or -2.5V ±5%, V
CC
= 0V, T
A
= -40°C to 85°C
Symbol
V
PP
V
CMR
f
CLK
t
PD
V
DIF
V
X
V
O
(pp)
tsk(o)
Parameter
Differential Input Voltage; NOTE 1
Differential Input Crosspoint Voltage;
NOTE 2
Input Frequency; NOTE 3
Propagation Delay, CLKA or CLKB to
Output Pair; NOTE 4
HSTL Differential Input Voltage;
NOTE 5
HSTL Input Differential Crosspoint
Voltage; NOTE 6
Differential Output Voltage
(peak-to-peak)
Output Skew
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Pulse Skew; NOTE 7
Output Rise/Fall Time
156.25MHz, @ 3.3V,
1.875MHz – 20MHz
312.5MHz @ 3.3V,
1.875MHz – 20MHz
660MHz
20% to 80%
0.05
0.114
0.052
75
0.3
ƒ
OUT
< 300MHz
ƒ
OUT
< 1.5GHz
230
0.4
V
EE
+ 0.01
0.45
0.3
0.88
0.74
Test Conditions
Minimum
0.15
V
EE
+ 1.0
Typical
Maximum
1.3
V
CC
- 0.3
2.7
650
1.0
V
CC
- 1.0
0.95
0.95
50
Units
V
V
GHz
ps
V
V
V
V
ps
ps
ps
ps
ns
tjit
tsk(p)
t
R
/ t
F
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: V
PP
is the minimum differential ECL/LVPECL input voltage swing required to maintain AC characteristics including t
PD
and
device-to-device skew.
NOTE 2: V
CMR
is the crosspoint of the differential ECL/LVPECL input signal. Normal AC operation is obtained when the crosspoint is within
the V
CMR
range and the input swing lies within the V
PP
specification. Violation of V
CMR
or V
PP
impacts the device propagation delay, device
and part-to-part skew.
NOTE 3: The IDT8T33FS314 is fully operational up to 2.7GHz and is characterized up to 1.5GHz.
NOTE 4: Propagation delay specified for output rise and fall times less than 5ns.
NOTE 5: V
DIF
is the minimum differential HSTL input voltage swing required to maintain AC characteristics including t
PD
and device-to-
device skew.
NOTE 6: V
X
is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the V
X
range and the input swing lies within the V
DIF
specification. Violation of V
X
or V
DIF
impacts the device propagation delay, device and
part-to-part skew.
NOTE 7: Output pulse skew is the absolute value of the difference of the propagation delay times:
t
PLH
– t
PHL
.
IDT8T33FS314PGI REVISION A MARCH 7, 2014
5
©2014 Integrated Device Technology, Inc.
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