DATASHEET
ISL70001SEH, ISL70001SRH
Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator
The
ISL70001SEH, ISL70001SRH
are radiation hardened and
SEE hardened high efficiency monolithic synchronous buck
regulators with integrated MOSFETs. This single chip power
solution operates over an input voltage range of 3V to 5.5V
and provides a tightly regulated output voltage that is
externally adjustable from 0.8V to ~85% of the input voltage.
Output load current capacity is 6A for T
J
< +145°C
.
High integration and class leading radiation tolerance makes
the ISL70001SEH, ISL70001SRH ideal choices to power
many of today’s small form factor applications. Two devices
can be synchronized to provide a complete power solution for
large scale digital ICs, like field programmable gate arrays
(FPGAs) that require separate core and I/O voltages.
In applications where the ENABLE input is tied high to PVIN we
recommend that the input voltage ramp rate be equal to or
greater than 10V/ms. This is to prevent unwanted voltage from
prematurely appearing on the output.
For a PVIN voltage that has a slower ramp rate or is stepped up
we recommend use of the
ISL70001ASEH.
Ensuring that the
ENABLE input is held low until the chosen VINPOR is satisfied
will prevent this ‘false start’.
FN7956
Rev 3.00
February 22, 2014
Features
• ±1% reference voltage over line, load, temperature and
radiation
• Current mode control for excellent dynamic response
• Full Mil-temp range operation (T
A
= -55°C to +125°C)
• High efficiency >90%
• Fixed 1MHz operating frequency
• Available in a thermally enhanced heatsink package - R48.B
• Operates from 3V to 5.5V supply
• Adjustable output voltage
- Two external resistors set V
OUT
from 0.8V to ~85% of V
IN
• Bidirectional SYNC pin allows two devices to be
synchronized 180° out-of-phase
• Starts into prebiased load
• Power-good output voltage monitor
• Adjustable analog soft-start
• Input undervoltage, output undervoltage and output
overcurrent protection
• Electrically screened to DLA SMD
5962-09225
• QML qualified per MIL-PRF-38535 requirements
• EH version is wafer-by-wafer acceptance tested for ELDRS
• Radiation hardness
- Total dose [50-300rad(Si)/s] . . . . . . . . . 100krad(Si) (min)
- Total dose [<10mrad(Si)/s] . . . . . . . . . . . .50krad(Si) (min)
• SEE hardness
- SEL and SEB LET
eff
. . . . . . . . . . . 86.4MeV/mg/cm
2
(min)
- SEFI X-section (LET
eff
= 86.4MeV/mg/cm
2
) 1.4 x 10
-6
cm
2
(max)
- SET LET
eff
(<1 pulse perturbation) 86.4MeV/mg/cm
2
(min)
Applications
• FPGA, CPLD, DSP, CPU core or I/O voltages
• Low-voltage, high-density distributed power systems
Related Literature
•
AN1518
ISL70001SRHEVAL1Z Evaluation Board,
•
Single Event Effects (SEE)
Testing of the ISL70001SRH
Synchronous Buck Regulator
•
Total Dose Testing
of the ISL70001SRH Hardened Point of
Load Regulator
95
90
ISL70001SEH
SYNCH
CORE
EFFICIENCY (%)
5V SUPPLY
85
ISL75051SEH
AUX
RAD TOLERANT
FPGA
80
75
ISL70001SEH
SYNCH
I/O
70
0
1
2
3
4
5
6
LOAD CURRENT (A)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. EFFICIENCY 5V INPUT TO 3.3V OUTPUT, T
A
= +25°C
FN7956 Rev 3.00
February 22, 2014
Page 1 of 21
ISL70001SEH, ISL70001SRH
Functional Block Diagram
AVDD
AGND
DVDD
DGND
EN
PORSEL
POWER-ON
RESET (POR)
PVINx
CURRENT
SENSE
SS
SOFT
START
SLOPE
COMPENSATION
PWM
CONTROL
LOGIC
FB
EA
GM
GATE
DRIVE
LXx
COMPENSATION
PGNDx
PGOOD
UV
POWER-GOOD
REF
PWM
REFERENCE
0.6V
TDI
BIT
TDO
TRIM
ZAP
SYNC
M/S
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN7956 Rev 3.00
February 22, 2014
Page 2 of 21
ISL70001SEH, ISL70001SRH
Ordering Information
ORDERING NUMBER
(Note
2)
5962R0922502VXC
5962R0922502VYC
5962R0922502V9A
5962R0922501VXC
5962R0922501QXC
5962R0922501V9A
ISL70001SRHF/PROTO
ISL70001SEHFE/PROTO
ISL70001SRHX/SAMPLE
ISL70001SRHEVAL1Z
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
Ordering Information table on must be used when ordering.
PART NUMBER
ISL70001SEHVF (Note
1)
ISL70001SEHVFE (Note
1)
ISL70001SEHVX
ISL70001SRHVF (Note
1)
ISL70001SRHQF (Note
1)
ISL70001SRHVX
ISL70001SRHF/PROTO (Note
1)
ISL70001SEHFE/PROTO (Note
1)
ISL70001SRHX/SAMPLE
Evaluation Board
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
(RoHS Compliant)
48 Ld CQFP
48 Ld CQFP With Heatsink
Die
48 Ld CQFP
48 Ld CQFP
Die
48 Ld CQFP
48 Ld CQFP With Heatsink
Die
R48.A
R48.B
R48.A
R48.A
PKG.
DWG. #
R48.A
R48.B
Pin Configuration
ISL70001SEH, ISL70001SRH
(48 LD CQFP)
TOP VIEW
PGND1
PGND1
PGND2
PGND2
PVIN1
PVIN1
PVIN2
PVIN2
PVIN3
SYNC
LX1
LX2
6
M/S
ZAP
TDI
TDO
PGOOD
SS
DVDD
DVDD
DGND
DGND
AGND
AGND
7
8
9
10
11
12
13
14
15
16
17
5
4
3
2
1 48 47 46 45 44 43
42
41
40
39
38
37
36
35
34
33
32
PVIN3
LX3
PGND3
PGND3
PGND4
PGND4
LX4
PVIN4
PVIN4
PVIN5
PVIN5
LX5
* HEATSINK
31
18
19 20 21 22 23 24 25 26 27 28 29 30
PORSEL
REF
FB
AVDD
EN
LX6
PGND6
PGND6
PGND5
PGND5
PVIN6
PVIN6
* Heatsink available in R48.B package
FN7956 Rev 3.00
February 22, 2014
Page 3 of 21
ISL70001SEH, ISL70001SRH
Pin Descriptions
PIN NUMBER
1, 2, 27, 28, 29, 30,
37, 38, 39, 40, 47,
48
3, 26, 31, 36, 41,
46
PIN NAME
PGNDx
DESCRIPTION
These pins are the power grounds associated with the corresponding internal power blocks. Connect these pins
directly to the ground plane. These pins should also connect to the negative terminals of the input and output
capacitors. Locate the input and output capacitors as close as possible to the IC.
These pins are the outputs of the corresponding internal power blocks and should be connected to the output
filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches. To minimize
voltage undershoot, it is recommended that a Schottky diode be connected from these pins to PGNDx. The
Schottky diode should be located as close as possible to the IC.
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be
connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly
to PGNDx with ceramic capacitors located as close as possible to the IC.
This pin is the synchronization I/O for the IC. When configured as an output (Master mode), this pin drives the
SYNC input of another ISL70001SEH, ISL70001SRH. When configured as an input (Slave mode), this pin
accepts the SYNC output from another ISL70001SEH, ISL70001SRH or an external clock. Synchronization of
the slave unit is 180° out-of-phase with respect to the master unit. If synchronizing to an external clock, the
clock must be SEE hardened and the frequency must be within the range of 1MHz ±20%.
This pin is the Master/Slave input for selecting the direction of the bidirectional SYNC pin. For SYNC = Output
(Master mode), connect this pin to DVDD. For SYNC = Input (Slave mode), connect this pin to DGND.
This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to DGND.
This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.
This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.
This pin is the power-good output. This pin is an open-drain logic output that is pulled to DGND when the output
voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,
independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin to
DGND with a 10nF ceramic capacitor to mitigate SEE.
This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output
ramp time in accordance with
Equation 1:
t
SS
=
C
SS
V
REF
I
SS
(EQ. 1)
LXx
4, 5, 24, 25, 32, 33,
34, 35, 42, 43, 44,
45
6
PVINx
SYNC
7
8
9
10
11
M/S
ZAP
TDI
TDO
PGOOD
12
SS
Where:
t
SS
= Soft-start output ramp time
C
SS
= Soft-start capacitor
V
REF
= Reference voltage (0.6V typical)
I
SS
= Soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms.
The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.
13, 14
DVDD
These pins are the bias supply inputs to the internal digital control circuitry. Connect these pins together at the
IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter
components as close as possible to the IC.
These pins are the digital ground associated with the internal digital control circuitry. Connect these pins
directly to the ground plane.
These pins are the analog ground associated with the internal analog control circuitry. Connect these pins
directly to the ground plane. Reference
“Metallization Mask Layout” on page 17,
pad 13 is labeled PGND and
is pin 17 on the packaged device. These 2 pads are to be connected together when using the die product.
This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω
resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC.
This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor
located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current (sourcing or
sinking) is available from this pin.
15, 16
17, 18
DGND
AGND
19
20
AVDD
REF
FN7956 Rev 3.00
February 22, 2014
Page 4 of 21
ISL70001SEH, ISL70001SRH
Pin Descriptions
(Continued)
PIN NUMBER
21
PIN NAME
FB
DESCRIPTION
This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and
from FB to AGND to adjust the output voltage in accordance with
Equation 2:
V
OUT
=
V
REF
1
+
R
T
R
B
(EQ. 2)
Where:
V
OUT
= Output voltage
V
REF
= Reference voltage (0.6V typical)
R
T
= Top divider resistor (Must be 1kΩ)
R
B
= Bottom divider resistor
The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across RT to mitigate
SEE and to improve stability margins.
22
EN
This pin is the enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and
programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND with a 10nF
ceramic capacitor to mitigate SEE.
This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V
supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply
voltages between 5V and 3.3V, connect this pin to DGND.
The heatsink is electrically isolated and should be connected to a thermal chassis of any potential which offers
optimal thermal relief.
23
PORSEL
Heatsink
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
ISL70001SEH
ISL70001SRH
LOW DOSE
Yes
No
FN7956 Rev 3.00
February 22, 2014
Page 5 of 21
Microchip MCU
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