Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulsed: Pulse Duration = 300
ms,
Duty Cycle = 2%
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2
BUV27
1.0
0.7
0.5
0.3
0.2
0.1
0.1
0.07
0.05
0.03
0.02
0.01
SINGLE PULSE
0.01
0.01
0.02
0.05
0.1
0.2
0.5
1.0
2.0
5.0
t, TIME (ms)
10
20
0.05
0.02
Z
qJC(t)
= r(t) R
qJC
R
qJC
= 1.785C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
C
= P
(pk)
Z
qJC(t)
r(t), TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
D = 0.5
0.2
t
2
DUTY CYCLE, D = t
1
/t
2
50
100
200
500 1.0 k
Figure 1. Thermal Response
,
C
I
COLLECTOR CURRENT (AMP)
20
16
10
100
ms
5 ms
dc
1.0
0.1
BONDING WIRE LIMITED
THERMALLY LIMITED
SECOND BREAKDOWN
LIMITED @ T
C
= 25°C
5.0
10
50
20
120 150
V
CE
, COLLECTOR−EMITTER VOLTAGE (V)
0.02
2.0
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
− V
CE
limits of the transistor that must be observed for reliable
operation, i.e., the transistor must not be subjected to greater
dissipation then the curves indicate.
The data of Figures 2 is based on T
J(pk)
= 150°C; T
C
is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
J(pk)
< 150°C. T
J(pk)
may be calculated from the data in Figure 1.
At high case temperatures, thermal limitations will reduce
the power that can be handled to values less than the
limitations imposed by second breakdown.
Figure 2. Forward Bias Safe Operating Area
T
A
PD, POWER DISSIPATION (WATTS)
T
C
3.0
60
2.0
40
T
C
1.0
20
T
A
0
0
0
20
40
60
80
100
120
140
160
T, TEMPERATURE (°C)
Figure 3. Power Derating
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3
BUV27
1000
V
CE
= 2 V
V
BE(ON)
, BASE−EMITTER ON
VOLTAGE (V)
h
FE
, DC CURRENT GAIN
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.1
1
10
100
T
A
= 150°C
T
A
= 25°C
T
A
= −55°C
V
CE
= 2 V
T
A
= 150°C
100
T
A
= 25°C
T
A
= −55°C
10
0.1
1
10
100
I
C
, COLLECTOR CURRENT (A)
V
BE(sat)
, BASE−EMITTER SATURATION VOLTAGE (V)
I
C
, COLLECTOR CURRENT (A)
Figure 4. DC Current Gain vs. Collector
Current
1.3
1.2
1.1
1
0.9 T
A
= −55°C
0.8
0.7
0.6
0.5
0.4
0.3
0.1
1
10
100
T
A
= 150°C
T
A
= 25°C
1
I
C
/I
B
= 10
V
CE(ON)
, COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
Figure 5. Base−Emitter Turn−ON Voltage vs.
Collector Current
I
C
/I
B
= 10
T
A
= 150°C
0.1
T
A
= 25°C
T
A
= −55°C
0.01
0.1
1
10
100
I
C
, COLLECTOR CURRENT (A)
I
C
, COLLECTOR CURRENT (A)
Figure 6. Base−Emitter Saturation Voltage vs.
Collector Current
10k
f
tau
, CURRENT−GAIN BANDWIDTH
PRODUCT (MHz)
80
70
60
50
40
30
20
10
Figure 7. Collector−Emitter Saturation Voltage
vs. Collector Current
V
CE
= 1 V
T
A
= 25°C
C, CAPACITANCE (pF)
C
ibo
1k
C
obo
100
10
0.1
1
10
100
0
0.1
1
I
C
, COLLECTOR CURRENT (A)
10
V
R
, REVERSE VOLTAGE (V)
Figure 8. Capacitance
Figure 9. Current Gain Bandwidth Product vs.
Collector Current
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4
BUV27
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AH
−T−
B
4
SEATING
PLANE
F
T
S
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.415
0.160
0.190
0.025
0.038
0.142
0.161
0.095
0.105
0.110
0.161
0.014
0.024
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
---
---
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.53
4.07
4.83
0.64
0.96
3.61
4.09
2.42
2.66
2.80
4.10
0.36
0.61
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
---
---
2.04
Q
1 2 3
A
U
K
H
Z
L
V
G
D
N
R
J
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
ON Semiconductor and the
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