74LVQ174
HEX D-TYPE FLIP FLOP WITH CLEAR
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 150 MHz (TYP.) at V
CC
= 3.3 V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
75Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3.0 V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
IMPROVED LATCH-UP IMMUNITY
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
DESCRIPTION
The 74LVQ174 is a low voltage CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
Figure 1: Pin Connection And IEC Logic Symbols
so
b
O
r
P
te
le
du
o
(s
ct
-
)
so
b
O
technology. It is ideal for low power and low noise
3.3V applications.
Information signals applied to D inputs are
transferred to the Q outputs on the positive going
edge of the CLK pulse.
When the CLR input is held low, the Q outputs are
held low independently of the other inputs.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
te
le
ro
P
uc
d
74LVQ174MTR
74LVQ174TTR
s)
t(
July 2004
Rev. 5
1/13
74LVQ174
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
PIN N°
1
2, 5, 7, 10,
12, 15
3, 4, 6, 11,
13, 14
9
8
16
SYMBOL
CLR
Q0 to Q5
D0 to D5
CLK
GND
V
CC
NAME AND FUNCTION
Asynchronous Master
Reset (Active LOW)
Flip-Flop Outputs
Data Inputs
Clock Input (Positive Edge
Triggered)
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
INPUTS
CLR
L
H
H
H
X : Don’t Care
OUTPUT
CLK
X
Q
L
L
H
Q
n
FUNCTION
D
X
L
H
X
Figure 3: Logic Diagram
so
b
O
r
P
te
le
du
o
(s
ct
-
)
so
b
O
te
le
ro
P
uc
d
CLEAR
s)
t(
NO CHANGE
This logic diagram has not to be used to estimate propagation delays
2/13
74LVQ174
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
300
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 3.0V (note 2)
Parameter
Value
2 to 3.6
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
Table 6: DC Specifications
Test Condition
Symbol
Parameter
V
CC
(V)
V
IH
V
IL
V
OH
b
O
V
OL
so
I
I
ro
P
te
le
Low Level Output
Voltage
Input Leakage
Current
Quiescent Supply
Current
Dynamic Output
Current (note 1, 2)
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
3.0 to
3.6
du
3.0
3.0
(s
ct
-
)
bs
O
Min.
2.0
et
l
o
P
e
Value
od
r
0 to 10
0 to V
CC
0 to V
CC
uc
s)
t(
Unit
V
V
V
°C
ns/V
-55 to 125
T
A
= 25°C
Typ.
Max.
-40 to 85°C
Min.
2.0
0.8
0.8
2.9
2.48
2.2
Max.
-55 to 125°C
Min.
2.0
0.8
2.9
2.48
2.2
Max.
Unit
V
V
I
O
=-50
µA
I
O
=-12 mA
I
O
=-24 mA
I
O
=50
µA
I
O
=12 mA
I
O
=24 mA
3.6
3.6
3.6
V
I
= V
CC
or GND
V
I
= V
CC
or GND
V
OLD
= 0.8 V max
V
OHD
= 2 V min
2.9
2.58
2.99
V
0.1
0.44
0.55
±
1
40
µA
µA
mA
mA
V
0.002
0
0.1
0.36
0.1
0.44
0.55
±
0.1
4
36
-25
±
1
40
25
-25
I
CC
I
OLD
I
OHD
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω
3/13
74LVQ174
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
C
L
= 50 pF
3.3
0.8
V
T
A
= 25°C
Min.
Typ.
0.3
-0.8
2
-0.3
Max.
0.8
V
V
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
Unit
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low
Voltage Quiet
Output (note 1, 2)
Dynamic High
Voltage Input
(note 1, 3)
Dynamic Low
Voltage Input
(note 1, 3)
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f=1MHz.
Table 8: AC Electrical Characteristics
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
T
A
= 25°C
Min.
Typ.
6.7
5.5
7.0
1.0
Max.
11.0
8.0
Value
-40 to 85°C
t
PLH
t
PHL
Propagation Delay
Time CK to Q
t
PHL
t
W(L)
t
W
Propagation Delay
Time CLR to Q
CLR Pulse Width,
LOW
CLOCK Pulse
Width, HIGH or
LOW
Setup Time D to
CK, HIGH or LOW
t
sL
t
sH
t
hL
t
hH
t
REM
f
MAX
b
O
t
OSLH
t
OSHL
so
ro
P
te
le
Hold Time D to CK,
HIGH or LOW
Recovery Time
CLR to CK
Maximum Clock
Frequency
Output To Output
Skew Time
(note1, 2)
du
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
2.7
3.3
(*)
(s
ct
-
)
so
b
O
8.3
4.0
1.0
3.0
4.0
3.0
4.0
3.0
3.0
2.0
3.0
2.0
60
90
1.0
1.0
0.5
0.4
et
l
P
e
Min.
4.0
3.0
4.0
3.0
4.0
3.0
3.0
2.0
3.0
2.0
50
70
ro
9.5
uc
d
Min.
s)
t(
Max.
14.5
11.0
18.0
13.0
-55 to 125°C
Unit
Max.
12.5
15.5
11.5
ns
ns
ns
13.5
10.0
5.0
4.0
5.0
4.0
4.0
3.0
3.0
2.0
3.0
2.0
50
70
1.0
1.0
1.0
1.0
ns
-0.5
-0.4
ns
ns
ns
MHz
-0.3
-0.3
150
150
0.5
0.5
1.0
1.0
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
4/13
74LVQ174
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
3.3
f
IN
= 10MHz
T
A
= 25°C
Min.
Typ.
4
23
Max.
Value
-40 to 85°C
Min.
Max.
-55 to 125°C
Min.
Max.
pF
pF
Unit
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/6 (per flip
flop)
Figure 4: Test Circuit
C
L
= 50pF or equivalent (includes jig and probe capacitance)
R
L
= R
1
= 500Ω or equivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
so
b
O
r
P
te
le
du
o
(s
ct
-
)
so
b
O
te
le
ro
P
uc
d
s)
t(
5/13
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