Low Skew, 1-to-16
Differential-to-LVDS Clock Distribution Chip
G
ENERAL
D
ESCRIPTION
The ICS8516 is a low skew, high performance 1-to-16 Differential-
to-LVDS Clock Distribution Chip.The ICS8516 CLK, nCLK pair can
accept any differential input levels and translates them to 3.3V LVDS
output levels. Utilizing Low Voltage Differential Signaling (LVDS),
the ICS8516 provides a low power, low noise, point-to-point
solution for distributing clock signals over controlled impedances
of 100Ω.
Dual output enable inputs allow the ICS8516 to be used in a
1-to-16 or 1-to-8 input/output mode.
Guaranteed output and part-to-part skew specifications make
the ICS8516 ideal for those applications demanding well
defined performance and repeatability.
ICS8516
DATASHEET
F
EATURES
•
Sixteen differential LVDS outputs
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
Maximum output frequency: 700MHz
•
Translates any differential input signal (LVPECL, LVHSTL,
SSTL, DCM) to LVDS levels without external bias networks
•
Translates any single-ended input signal to LVDS
with resistor bias on nCLK input
•
Multiple output enable inputs for disabling unused
outputs in reduced fanout applications
•
LVDS compatible
•
Output skew: 90ps (maximum)
•
Part-to-part skew: 500ps (maximum)
•
Propagation delay: 2.4ns (maximum)
•
Additive phase jitter, RMS: 148fs (typical)
•
3.3V operating supply
•
0°C to 70°C ambient operating temperature
•
Available in lead-free RoHS compliant package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
48-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
8516 REVISION B 6/11/15
1
©2015 Integrated Device Technology, Inc.
8516 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6, 12,
25, 31, 36
2, 3
4, 5
7, 17, 20,
30, 41, 44
8, 9
10, 11
13, 14
15, 16
18
19
21, 22
23, 24
26, 27
28, 29
32, 33
34, 35
37, 38
39, 40
42, 43
45, 46
47, 48
Name
V
DD
nQ5, Q5
nQ4, Q4
GND
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
nCLK
CLK
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Q11, nQ11
Q10, nQ10
Q9, nQ9
Q8, nQ8
OE2, OE1
nQ7, Q7
nQ6, Q6
Power
Output
Output
Power
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Input
Output
Output
Pullup
Pullup
Pulldown
Type
Description
Positive supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power supply ground.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inverting differential clock input.
Non-inverting differential clock input.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15; OE1
controls outputs Q0, nQ0 thru Q7, nQ7.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
2
REVISION B 6/11/15
8516 DATA SHEET
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Test Conditions
Minimum
Typical
4
51
51
4
Maximum
Units
pF
kΩ
kΩ
pF
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
OE1
0
1
0
1
OE2
0
0
1
1
Q0:Q7
Hi Z
ACTIVE
Hi Z
ACTIVE
nQ0:nQ7
Hi Z
ACTIVE
Hi Z
ACTIVE
Outputs
Q8:Q15
Hi Z
Hi Z
ACTIVE
ACTIVE
nQ8:nQ15
Hi Z
Hi Z
ACTIVE
ACTIVE
In the active mode, the state of the outputs are a function of the CLK and nCLK inputs as described in Table 3B.
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
Q0:Q15
nQ0:nQ15
LOW
HIGH
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
REVISION B 6/11/15
3
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
8516 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Static Power Supply Current
RL = 100Ω
No Load
Test Conditions
Minimum
3.135
Typical
3.3
135
60
Maximum
3.465
165
75
Units
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE1, OE2
OE1, OE2
OE1, OE2
OE1, OE2
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Voltage
Common Mode Input Voltage;
GND + 0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined ast V
IH
.
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
4
REVISION B 6/11/15
8516 DATA SHEET
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
High Impedance Leakage Current
Power Off Leakage
Differential Output Short Circuit Current
Output Short Circuit Current
Test Conditions
Minimum
250
1.125
-10
-1
Typical
400
1.4
Maximum
600
50
1.6
50
+10
+1
-5.5
-12
Units
mV
mV
V
mV
µA
µA
mA
mA
V
OS
Δ
V
OS
I
OZ
I
OFF
I
OSD
I
OS
/I
OSB
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
R
/t
F
odc
t
PZL
, t
PZH
t
PLZ
, t
PHZ
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
Integration Range:
12kHz - 20MHz
20% to 80%
100
45
50
148
550
55
5
5
1.6
2.0
Test Conditions
Minimum
Typical
Maximum
700
2.4
90
500
Units
MHz
ns
ps
ps
fs
ps
%
ns
ns
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
REVISION B 6/11/15
5
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
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