MC74HC157A
Quad 2-Input Data
Selectors/Multiplexers
High−Performance Silicon−Gate CMOS
The MC74HC157A is identical in pinout to the LS157. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device routes 2 nibbles (A or B) to a single port (Y) as
determined by the Select input. The data is presented at the outputs in
noninverted form. A high level on the Output Enable input sets all four
Y outputs to a low level.
Features
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SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
•
•
•
•
•
•
PIN ASSIGNMENT
SELECT
A0
B0
Y0
A1
B1
Y1
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
OUTPUT
ENABLE
A3
B3
Y3
A2
B2
Y2
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
•
Chip Complexity: 82 FETs or 20.5 Equivalent Gates
•
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAMS
16
HC157AG
AWLYWW
1
SOIC−16
1
TSSOP−16
16
HC
157A
ALYWG
G
A0
NIBBLE
A INPUTS
A1
A2
A3
B0
NIBBLE
B INPUTS
B1
B2
B3
2
5
11
14
3
6
10
13
1
15
PIN 16 = V
CC
PIN 8 = GND
4
7
9
12
Y0
Y1
Y2
Y3
DATA
OUTPUTS
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
Enable
H
L
L
Select
X
L
H
Outputs
Y0 − Y3
L
A0 −A3
B0 −B3
SELECT
OUTPUT
ENABLE
Figure 1. Logic Diagram
X = don’t care
A0−A3, B0−B3 = the levels of
the respective Data−Word
Inputs.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 12
Publication Order Number:
MC74HC157A/D
MC74HC157A
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MAXIMUM RATINGS
Symbol
V
CC
V
in
Parameter
Value
Unit
V
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±20
±25
±50
V
out
I
in
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
mA
mA
mA
I
out
DC Output Current, per Pin
I
CC
P
D
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
SOIC Package†
TSSOP Package†
500
450
mW
_C
_C
T
stg
T
L
– 65 to + 150
260
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
–55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MC74HC157A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
V
out
= V
CC
– 0.1 V
|I
out
|
v
20
mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
6.0
6.0
–55 to
25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
±0.5
v
85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
±5.0
v
125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
±1.0
±10
mA
mA
V
Unit
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
|I
out
|
v
20
mA
V
in
= V
IH
V
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IL
|I
out
|
v
20
mA
V
in
= V
IL
I
in
I
OZ
Maximum Input Leakage Current
Maximum Three−State Leakage
Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
I
CC
6.0
4.0
40
160
mA
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 4)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
−
–55 to
25_C
105
65
21
18
110
70
22
19
100
60
20
17
75
27
15
13
10
v
85_C
130
85
26
22
140
90
28
24
125
80
25
21
95
32
19
16
10
v
125_C
160
115
32
27
165
115
33
28
150
110
30
26
110
36
22
19
10
Unit
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Select to Output Y
(Figures 2 and 4)
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Output Enable to Output Y
(Figures 3 and 4)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
ns
C
in
Maximum Input Capacitance
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
33
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
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3
MC74HC157A
PIN DESCRIPTIONS
INPUTS
A0, A1, A2, A3 (Pins 2, 5, 11, 14)
Nibble A inputs. The data present on these pins is
transferred to the outputs when the Select input is at a low
level and the Output Enable input is at a low level. The data
is presented to the outputs in noninverted form.
B0, B1, B2, B3 (Pins 3, 6, 10, 13)
The data present on these pins is in its noninverted form. For
the Output Enable input at a high level, the outputs are at a
low level.
CONTROL INPUTS
Select (Pin 1)
Nibble B inputs. The data present on these pins is
transferred to the outputs when the Select input is at a high
level and the Output Enable input is at a low level. The data
is presented to the outputs in noninverted form.
OUTPUTS
Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
Nibble select. This input determines the data word to be
transferred to the outputs. A low level on this input selects
the A inputs and a high level selects the B inputs.
Output Enable (Pin 15)
Output Enable input. A low level on this input allows the
selected input data to be presented at the outputs. A high
level on this input sets all outputs to a low level.
Data outputs. The selected input Nibble is presented at
these outputs when the Output Enable input is at a low level.
SWITCHING WAVEFORMS
t
r
INPUT A OR B
t
PLH
OUTPUT Y
t
TLH
90%
50%
10%
t
THL
90%
50%
10%
t
PHL
t
f
V
CC
SELECT
GND
t
PLH
OUTPUT Y
t
TLH
90%
50%
10%
t
THL
t
r
90%
50%
10%
t
PHL
t
f
V
CC
GND
Figure 2. HC157A
t
r
OUTPUT
ENABLE
t
PHL
OUTPUT Y
t
THL
90%
50%
10%
90%
50%
10%
Figure 3. Y versus Selected, Noninverted
t
f
V
CC
GND
t
PLH
t
TLH
Figure 4. HC157A
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
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4
MC74HC157A
EXPANDED LOGIC DIAGRAM
2
A0
B0
A1
B1
NIBBLE
OUTPUTS
A2
B2
A3
B3
OUTPUT ENABLE
SELECT
10
14
13
15
1
12 Y3
9 Y2
3
5
6
11
7
Y1
DATA
OUTPUTS
4
Y0
ORDERING INFORMATION
Device
MC74HC157ADG
MC74HC157ADR2G
MC74HC157ADTR2G
NLV74HC157ADR2G*
NLV74HC157ADTR2G*
Package
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
TSSOP−16
(Pb−Free)
SOIC−16
(Pb−Free)
TSSOP−16
(Pb−Free)
Shipping
†
48 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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