MC10EP445, MC100EP445
3.3V/5V ECL 8-Bit
Serial/Parallel Converter
Description
The MC10/100EP445 is an integrated 8–bit differential serial to
parallel data converter with asynchronous data synchronization. The
device has two modes of operation. CKSEL HIGH mode is designed
to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode
is designed to operate at twice the internal clock data rate of up to
5.0 Gb/s. The conversion sequence was chosen to convert the first
serial bit to Q0, the second bit to Q1, etc. Two selectable differential
serial inputs, which are selected by SINSEL, provide this device with
loop−back testing capability. The MC10/100EP445 has a SYNC pin
which, when held high for at least two consecutive clock cycles, will
swallow one bit of data shifting the start of the conversion data from
D
n
to D
n+1
. Each additional shift requires an additional pulse to be
applied to the SYNC pin.
Control pins are provided to reset and disable internal clock
circuitry. Additionally, V
BB
pin is provided for single−ended input
condition.
The 100 Series contains temperature compensation.
Features
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MARKING
DIAGRAM*
LQFP−32
FA SUFFIX
CASE 873A
MCxxx
EP445
AWLYYWWG
1
1
32
•
•
•
•
•
•
•
•
•
•
•
1530 ps Propagation Delay
5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode
Differential Clock and Serial Inputs
V
BB
Output for Single-Ended Input Applications
Asynchronous Data Synchronization (SYNC)
Asynchronous Master Reset (RESET)
PECL Mode Operating Range: V
CC
= 3.0 V to 5.5 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −3.0 V to −5.5 V
Open Input Default State
CLK ENABLE Immune to Runt Pulse Generation
These Devices are Pb−Free and are RoHS Compliant
QFN32
MN SUFFIX
CASE 488AM
MCxx
EP445
AWLYYWWG
G
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
June, 2014 − Rev. 16
Publication Order Number:
MC10EP445/D
MC10EP445, MC100EP445
V
CC
SINA SINA V
BB0
V
EE
SINB SINB SINSEL
32
RESET
SYNC
CKEN
CLK
CLK
V
BB1
CKSEL
V
CC
1
2
3
4
5
6
7
8
9
31
30
29
28
27
26
25
24
23
22
21
V
CC
PCLK
PCLK
Q0
V
CC
Q1
Q2
V
CC
MC10EP445
MC100EP445
20
19
18
17
10
11
12
13
14
15
16
Q7
Q6
Q5 V
CC
V
CC
Q4 Q3 V
EE
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. 32−Lead LQFP Pinout
(Top View)
Table 1. PIN DESCRIPTION
Exposed Pad
(EP)
V
CC
SINA SINA V
BB0
V
EE
SINB SINB SINSEL
32
RESET
SYNC
CKEN
CLK
CLK
V
BB1
CKSEL
V
CC
1
2
3
4
5
6
7
8
9
Q7
10
Q6
11
12
13
14
15
16
31
30
29
28
27
26
25
24
V
CC
23
PCLK
22
PCLK
21
Q0
Pin
SINA*, SINA*
SINB*, SINB*
SINSEL*
Q0−Q7
CLK*, CLK*
PCLK, PCLK
SYNC*
CKSEL*
CKEN*
19
Q1
18
Q2
17
V
CC
RESET*
V
BB0
, V
BB1
V
CC
V
EE
EP
Function
ECL Differential Serial Data Input A
ECL Differential Serial Data Input B
ECL Serial Input Selector Pin
ECL Parallel Data Outputs
ECL Differential Clock Inputs
ECL Differential Parallel Clock Output
ECL Conversion Synchronizing Input
ECL Clock Input Selector Pin
ECL Clock Enable Pin
ECL Reset Pin
Output Reference Voltage
Positive Supply
Negative Supply
The exposed pad (EP) on the QFN−32
package bottom is thermally connected
to the die for improved heat transfer out
of the package. THe exposed pad must
be attached to a heat−sinking conduit.
The pad is electrically connected to
V
EE
.
MC10EP445
MC100EP445
20
V
CC
Q5 V
CC
V
CC
Q4 Q3 V
EE
Figure 2. 32−Lead QFN Pinout
(Top View)
* Pins will default logic LOW or differential logic LOW
when left open.
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2
MC10EP445, MC100EP445
Table 2. TRUTH TABLE
FUNCTION
PIN
SINSEL
CKSEL
Select SINB Input
Q: PCLK = 8:1
CLK: Q = 1:1
CLK
Q
CKEN
RESET
SYNC
Synchronously Disable Internal Clock Circuitry
Asynchronous Master Reset
Asynchronously Applied to Swallow a Data Bit
High
Low
Select SINA Input
Q: PCLK = 8:1
CLK: Q = 1:2
CLK
Q
Synchronously Enable Internal
Clock Circuitry
Synchronous Enable
Normal Conversion Process
SINA
V
EE
SINA
SINB
SINB
SINSEL
1:2
DEMUX
CKEN
T
C
R
Q
1:2
DEMUX
1:2
DEMUX
Q1
Q5
Q3
Q7
Control
Logic
CLK
DIV2
DIV2
PCLK
PCLK
1:2
DEMUX
1:2
DEMUX
1:2
DEMUX
Q0
Q4
Q2
Q6
T
C
R
Q
SYNC
1:2
DEMUX
CLK
CKSEL
RESET
Figure 3. Logic Diagram
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3
MC10EP445, MC100EP445
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pull−up Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Pb Pkg
Level 2
N/A
Value
75 kW
N/A
> 2 kV
> 200 V
> 2 kV
Pb−Free Pkg
Level 2
Level 1
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
LQFP−32
QFN−32
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
993 Devices
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
I
BB
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
2S2P
<2 to 3 sec @ 260°C
32 LQFP
32 LQFP
32 LQFP
QFN−32
QFN−32
QFN−32
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
6
−6
6
−6
50
100
±
0.5
−40 to +85
−65 to +150
80
55
12 to 17
31
27
12
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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MC10EP445, MC100EP445
Table 5. 10EP DC CHARACTERISTICS, PECL
V
CC
= 3.3 V, V
EE
= 0 V (Note 2)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
Input HIGH Current
Input LOW Current
0.5
Min
95
2165
1365
2090
1365
1790
2.0
1890
Typ
119
2290
1490
Max
143
2415
1615
2415
1690
1990
3.3
Min
98
2230
1430
2155
1460
1855
2.0
1955
25°C
Typ
122
2355
1555
Max
146
2480
1680
2480
1755
2055
3.3
Min
100
2290
1490
2215
1490
1915
2.0
2015
85°C
Typ
125
2415
1615
Max
150
2540
1740
2540
1815
2115
3.3
Unit
mA
mV
mV
mV
mV
mV
V
I
IH
I
IL
150
0.5
150
0.5
150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.3 V to −2.2 V.
3. All loading with 50
W
to V
CC
− 2.0 V.
4. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
Table 6. 10EP DC CHARACTERISTICS, PECL
V
CC
= 5.0 V, V
EE
= 0 V (Note 5)
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current (Note 6)
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 8)
Input HIGH Current
Input LOW Current
0.5
Min
95
3865
3065
3790
3065
3490
2.0
3590
Typ
119
3990
3190
Max
143
4115
3315
4115
3390
3690
5.0
Min
98
3930
3130
3855
3130
3555
2.0
3655
25°C
Typ
122
4055
3255
Max
146
4180
3380
4180
3455
3755
5.0
Min
100
3990
3190
3915
3190
3615
2.0
3715
85°C
Typ
125
4115
3315
Max
150
4240
3440
4240
3515
3815
5.0
Unit
mA
mV
mV
mV
mV
mV
V
I
IH
I
IL
150
0.5
150
0.5
150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +2.0 V to −0.5 V.
6. Required 500 lfpm air flow when using +5 V power supply. For (V
CC
− V
EE
) >3.3 V, 5
W
to 10
W
in line with V
EE
required for maximum thermal
protection at elevated temperatures. Recommend V
CC
−V
EE
operation at
3.3 V.
7. All loading with 50
W
to V
CC
− 2.0 V.
8. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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