19-1631; Rev 0a; 8/01
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
General Description
The MAX3876 is a compact, low-power clock recovery
and data retiming IC for 2.488Gbps SDH/SONET appli-
cations. The fully integrated phase-locked loop (PLL)
recovers a synchronous clock signal from the serial
NRZ data input. The data is retimed by the recovered
clock. Differential CML outputs are provided for both
clock and data signals, and an additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor.
The MAX3876 is designed for both section-regenerator
and terminal-receiver applications in OC-48/STM-16
transmission systems. Its jitter performance exceeds all
of the SONET/SDH specifications.
This device operates from a +3.3V or +5.0V single sup-
ply over a -40°C to +85°C temperature range. Power
consumption is typically only 445mW with a +3.3V sup-
ply. The MAX3876 is available in a 32-pin TQFP pack-
age as well as in die form.
Features
o
Exceeds ANSI, ITU, and Bellcore SONET/SDH
Regenerator Specifications
o
440mW Power Dissipation (at +3.3V)
o
Clock Jitter Generation: 3.7mUI
RMS
o
+3.3V or +5V Single Power Supply
o
Fully Integrated Clock Recovery and Data Retiming
o
Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
o
Tolerates >2500 Consecutive Identical Digits
o
Loss-of-Lock Indicator
o
Differential CML Data and Clock Outputs
MAX3876
Applications
SDH/SONET Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
2.488Gbps ATM Receiver
Digital Video Transmission
SDH/SONET Test Equipment
Intrarack/Subrack Interconnects
PART
MAX3876EHJ
MAX3876E/D
Ordering Information
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Dice*
*Dice
are designed to operate over this range, but are tested
and guaranteed at T
A
= +25°C only. Contact factory for
availability.
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
0.01µF
V
CC
FILT
PHOTO-
DIODE
0.01µF
IN
V
CC
OUT+
SDI+
SDO+
SDO-
LOL
+3.3V
TTL
+3.3V
MAX3866
PREAMPLIFIER
OUT-
SDI-
SLBI+
SLBI-
SIS
FIL+
FIL-
SCLKO+
SCLKO-
MAX3876
MAX3831
4:1/1:4
TRANSCEIVER
SYSTEM
LOOPBACK
TTL
1µF
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
MAX3876
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
..............................................-0.5V to +7.0V
Input Voltage Levels
(SDI+, SDI-, SLBI+, SLBI-) ...........(V
CC
- 0.5V) to (V
CC
+ 0.5V)
Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±11mA
CML Output Current Levels
(SDO+, SDO-, SCLKO+, SCLKO-) ................................±22mA
Voltage at
LOL,
SIS, FIL+, FIL-...................-0.5V to (V
CC
+ 0.5V)
Continuous Power Dissipation (T
A
= +85°C)
32-Pin TQFP (derate 16.1mW/°C above +85°C).............1.0W
Operating Temperature Range
MAX3876EHJ..................................................-40°C to +85°C
Operating Junction Temperature Range (die) ..-55°C to +150°C
Storage Temperature Range .............................-60°C to +160°C
Processing Temperature (die) .........................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +5.5V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and T
A
= +25°C.) (Note 1)
PARAMETER
Supply Current
Input Common-Mode Voltage
Differential Input Voltage
(SDI±, SLBI±)
Single-Ended Input Voltage
(SDI±, SLBI±)
Input Termination to V
CC
(SDI±, SLBI±)
CML Differential Output Voltage
Swing
Differential Output Impedance
CML Output Common-Mode
Voltage
TTL Input High Voltage (SIS)
TTL Input Low Voltage (SIS)
TTL Input Current (SIS)
TTL Output High Voltage (LOL)
TTL Output Low Voltage (LOL)
V
OH
V
OL
V
IH
V
IL
-10
2.4
R
L
= 50Ω to V
CC
2.0
0.8
+10
V
CC
0.4
SYMBOL
I
CC
V
CM
V
ID
V
IS
R
IN
R
L
= 50Ω to V
CC
T
A
= 0°C to +85°C
T
A
= -40°C
640
580
85
DC-coupled
Figure 1, DC-coupled
Figure 1, AC-coupled
CONDITIONS
Excluding CML output termination
V
CC
- 0.25
50
50
V
CC
- 0.4
48
800
800
100
V
CC
- 0.2
1000
1000
115
1000
1600
V
CC
+ 0.4
MIN
TYP
135
MAX
167
UNITS
mA
V
mVp-p
V
Ω
mVp-p
Ω
V
V
V
µA
V
V
V
CC
+ 0.4V
800mV
V
CC
25mV
t
CK
V
CC
- 0.4V
V
CC
(a)
AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)
25mV
SCLKO+
t
CK-Q
SDO
500mV
V
CC
- 0.25V
V
CC
- 0.5V
(b)
DC-COUPLED SINGLE-ENDED CML INPUT
Figure 1. Input Amplitude
2
Figure 2. Output Clock-to-Q Delay
_______________________________________________________________________________________
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +5.5V, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and T
A
= +25°C.) (Note 2)
PARAMETER
Serial Output Clock Rate
Clock-to-Q Delay
Jitter Peaking
Jitter Transfer Bandwidth
J
P
J
BW
f = 70kHz (Note 3)
Jitter Tolerance
f = 100kHz
f = 1MHz
f = 10MHz
Jitter Generation
Clock Output Edge Speed
Data Output Edge Speed
Tolerated Consecutive
Identical Digits
Input Return Loss
(SDI±, SLBI±)
100kHz to 2.5GHz
2.5GHz to 4.0GHz
J
GEN
Jitter BW = 12kHz to 20MHz
20% to 80%
20% to 80%
2.1
1.76
0.41
0.32
Figure 2
f
≤
2MHz
110
0.03
1.4
4.4
3.32
0.74
0.51
3.7
19.2
75
95
2500
17
15
6.2
61.0
mUI
RMS
mUIp-p
ps
ps
Bits
dB
UIp-p
SYMBOL
CONDITIONS
MIN
TYP
2.488
290
0.1
2.0
MAX
UNITS
GHz
ps
dB
MHz
MAX3876
Note 1:
Dice are tested at T
A
= +25°C only.
Note 2:
AC characteristics are guaranteed by design and characterization.
Note 3:
At jitter frequencies < 70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications.
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
RECOVERED DATA AND CLOCK
(DIFFERENTIAL OUTPUT)
MAX3876 toc1
RECOVERED CLOCK JITTER
MAX3876 toc2
JITTER TOLERANCE
MAX3876 toc03
2
23
-1 PATTERN
V
IN
= 50mVp-p
T
A
= +25°C
DATA
PRBS = 2
23
-1
V
IN
= 50mVp-p
WIDEBAND JITTER
= 3.94ps
RMS
10
INPUT JITTER (UIp-p)
200mV/div
50mV/div
1
BELLCORE
MASK
CLOCK
PRBS = 2
23
- 1
50mVp-p INPUT
0.1
100ps/div
10ps/div
10k
100k
1M
10M
JITTER FREQUENCY (kHz)
_______________________________________________________________________________________
3
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
MAX3876
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
JITTER TOLERANCE vs.
INPUT AMPLITUDE
JITTER FREQUENCY = 1MHz
0.8
JITTER TOLERANCE (UIp-p)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
100
INPUT SIGNAL AMPLITUDE (mVp-p)
1000
T
A
= +85°C
PRBS = 2
23
- 1
-2.5
PRBS = 2
23
- 1
-3.0
1k
10k
100k
1M
10M
JITTER FREQUENCY (Hz)
PRBS = 2
23
- 1
10
-10
8.8 8.9 9.0 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8
INPUT SIGNAL AMPLITUDE (mVp-p)
JITTER FREQUENCY = 5MHz
MAX3876 toc04
JITTER TRANSFER
MAX3876 toc05
BIT ERROR RATE vs.
INPUT AMPLITUDE
MAX3876 toc06
0.9
0.5
0
JITTER TRANSFER (dB)
-0.5
-1.0
-1.5
-2.0
BELLCORE
MASK
10
-5
10
-6
BIT ERROR RATE
10
-7
10
-8
10
-9
JITTER TOLERANCE
vs. PULSE-WIDTH DISTORTION
100kHz
PRBS = 2
23
- 1
100mVp-p INPUT
MAX3876 toc07
SUPPLY CURRENT
vs. TEMPERATURE
155
SUPPLY CURRENT (mA)
150
V
CC
= 5.0V
145
140
135
130
V
CC
= 3.0V
MAX3876 toc08
10
160
JITTER TOLERANCE (UI)
1MHz
1.0
10MHz
0.1
0
0.05
0.10
0.15
0.20
0.25
PULSE-WIDTH DISTORTION (UI)
125
120
-50
-25
0
25
50
75
100
AMBIENT TEMPERATURE (°C)
Pin Description
PIN
1, 2, 8, 9,
10, 16, 26,
29, 32
3, 6, 11,
14, 15, 17,
20, 21, 24,
27, 28
4
5
7
12
13
18
NAME
GND
Supply Ground
FUNCTION
V
CC
SDI+
SDI-
SIS
SLBI+
SLBI-
SCLKO-
Positive Supply Voltage
Positive Data Input. 2.488Gbps serial-data stream.
Negative Data Input. 2.488Gbps serial-data stream.
Signal Input Selection, TTL. Low for normal data input. High for system loopback input.
Positive System Loopback Input. 2.488Gbps serial-data stream.
Negative System Loopback Input. 2.488Gbps serial-data stream.
Negative Serial Clock Output, CML, 2.488GHz. SDO- is clocked out on the falling edge of SCLKO-.
4
_______________________________________________________________________________________
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
Pin Description (continued)
PIN
19
22
23
25
30
31
NAME
SCLKO+
SDO-
SDO+
LOL
FIL-
FIL+
Negative Data Output, CML, 2.488Gbps
Positive Data Output, CML, 2.488Gbps
Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10kΩ pull-up resistor)
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
FUNCTION
Positive Serial Clock Output, CML, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.
MAX3876
SIS
FIL+
FIL-
SDO+
SDI+
AMP
SDI-
MUX
SLBI+
AMP
SLBI-
LOL
TTL
PHASE AND
FREQUENCY
DETECTOR
LOOP
FILTER
I
VCO
Q
CML
SCLKO+
SCLKO-
D
CK
Q
CML
SDO-
MAX3876
Figure 3. Functional Diagram
Detailed Description
The MAX3876 consists of a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
and CML output buffer (Figure 3). The PLL consists of
a phase/frequency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO).
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
up to 1000mVp-p. With AC-coupling, differential input
signal amplitudes can be increased to a maximum of
1600mVp-p. The bit error rate is better than 1
·
10
-10
for
input signals as small as 10mVp-p, though the jitter tol-
erance performance will be degraded. For interfacing
with PECL signal levels, see
Applications Information.
Phase Detector
The phase detector incorporated in the MAX3876 pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming.
Input Amplifier
Input amplifiers are implemented for both the main data
and system loopback inputs. These amplifiers accept
DC-coupled differential input amplitudes from 50mVp-p
_______________________________________________________________________________________
5
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