DATASHEET
ISL8126
Dual/n-Phase Buck PWM Controller with Integrated Drivers
The ISL8126 integrates two voltage-mode PWM leading-edge
modulation control with input feed-forward synchronous buck
PWM controllers to control dual independent voltage
regulators or a 2-phase single output regulator. It also
integrates current sharing control for the power module to
operate in parallel, which offers high system flexibility.
The ISL8126 integrates an internal linear regulator, which
generates IC’s bias voltages for applications with only one
single supply rail. The internal oscillator is adjustable from
150kHz to 1.5MHz, and is able to synchronize to an external
clock signal for frequency synchronization and phase
paralleling applications. Its PLL circuit can output a
phase-shift-programmable clock signal for the system to be
expanded to 3-, 4-, 6- and 12- phases with desired interleaving
phase shift.
The ISL8126’s Fault Spreading feature protects any channel
from overloading/stressing due to system faults or phase
failure. The undervoltage fault protection features are also
designed to prevent a negative transient on the output voltage
during falling down. This eliminates the Schottky diode that is
used in some systems for protecting the load device from
reversed output voltage damage.
FN7892
Rev.2.00
January 29, 2015
Features
• Wide V
IN
range operation: 3V to 26.5V
- VCC operation from 3V to 5.60V
• Excellent output voltage regulation: 0.6V internal reference
• Frequency synchronization with programmable phase delay
up to 12-phase applications
• Fault spreading capability for high system reliability
• Digital soft-start with precharged output start-up capability
• Dual independent channel enable inputs with precision
voltage monitor and voltage feed-forward capability
- Programmable input voltage POR and its hysteresis with a
resistor divider at EN input
• Extensive circuit protection functions: output overvoltage,
undervoltage, overcurrent protection, over-temperature and
pre-power-on-reset overvoltage protection option
Applications
• Power supply for Datacom/Telecom and POL
• Paralleling power module
• Wide and narrow input voltage range buck regulators
Related Literature
•
TB389
“PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages”
•
AN1713,
“ISL8126EVAL1Z Evaluation Board User Guide”
VO1
0
o
VO
VIN
VIN
0
o
Vo
VIN
VO2
180
o
180
o
270
o
DUAL REGULATOR
TWO-PHASE REGULATOR
FOUR-PHASE REGULATOR
FIGURE 1. TYPICAL APPLICATION DIAGRAM
FN7892 Rev.2.00
January 29, 2015
Page 1 of 39
ISL8126
ISL8126
ISL8126
ISL8126
90
o
ISL8126
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Integrated Driver Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2-Phase Operation with DCR Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2-Phase Operation with rDS(ON) Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Dual Regulators with DCR Sensing and Remote Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Double Data Rate I or II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3-Phase Regulator with Precision Resistor Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4-Phase Operation with DCR Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Multiple Power Modules in Parallel with Current Sharing Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3-Phase Regulator with Resistor Sensing and 1-Phase Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6-Phase Operation with DCR Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Feed-forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRE-POR Overvoltage Protection (PRE-POR-OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature Protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sharing Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Share Control in Multiphase Single Output with Shared COMP Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Share Control Loop in Multi-Module with Independent Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Series Linear and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Synchronization and Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Amplifier for Remote Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Reference and System Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR and Dual Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Routing UGATE, LGATE and PHASE Traces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense Component Placement and Trace Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General PowerPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
25
26
28
28
29
30
31
32
32
33
33
34
35
36
36
37
37
37
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FN7892 Rev.2.00
January 29, 2015
Page 2 of 39
ISL8126
Pin Configuration
ISL8126
(32 LD QFN)
TOP VIEW
VSEN1+
ISEN1B
ISEN1A
VSEN1-
VMON1
BOOT1
25
24 UGATE1
23 PHASE1
22 LGATE1
21 PVCC
GND
20 LGATE2
19 PHASE2
18 UGATE2
17 BOOT2
9
COMP2
10
FB2
11
VMON2
12
VSEN2-
13
VSEN2+
14
ISEN2B
15
ISEN2A
16
VIN
VCC
26
FB1
32
COMP1
ISET
ISHARE
EN/VFF1
FSYNC
EN/VFF2
CLKOUT/REFIN
PGOOD
1
2
3
4
5
6
7
8
31
30
29
28
27
Functional Pin Descriptions
PIN
NUMBER
1, 9
SYMBOL
COMP1, COMP2
DESCRIPTION
These pins are the error amplifier outputs. They should be connected to FB1, FB2 pins through desired
compensation networks when both channels are operating independently. When VSEN1-, VSEN2- are
pulled within 400mV of VCC, the corresponding error amplifier is disabled and its output (COMP pin) is high
impedance. Thus, in multiphase operations, all other SLAVE phases’ COMP pins can tie to the MASTER
phase’s COMP1 pin (1st phase), which modulates each phase’s PWM pulse with a single voltage feedback
loop. While the error amplifier is not disabled, an independent compensation network is required for each
cascaded IC.
This pin along with ISHARE pin are used for multiple ISL8126 current sharing purposes. When in 2-phase
mode (VSEN2- pulled within 400mV of VCC), this pin sources a current which is a combination of 15µA
constant offset current, current correction current (more details on
“Current Share Control in Multiphase
Single Output with Shared COMP Voltage” on page 31),
and the average of both sensed channel currents.
When in Dual-output mode, this pin sources a current, which is a combination of 15µA constant offset
current, current correction current and Channel 1’s sensed current. The current sourced out from this pin
and an external resistor (RISET) set the voltage at this pin (VISET). The RISET is recommended to be 10kΩ.
A noise decoupling capacitor less than 100pF can be added in parallel with the 10kΩ RISET.
In the single IC configuration (both 2-phase mode and dual-output mode), this pin can be tied to the ISHARE
pin.
This pin is used for current sharing purposes and is configured to the current share bus representing all
modules’ average current. When in 2-phase mode (VSEN2- pulled within 400mV of VCC), this pin sources
a current, which is a combination of 15µA constant offset current and the average of both sensed channel
currents. When in Dual-output mode, this pin sources a current, which is a combination of 15µA constant
offset current and Channel 1’s sensed current.
The share bus (ISHARE pins connected together) voltage (VISHARE) set by an external resistor (RISHARE)
represents the average current level of all ISL8126 controller connected to the current share bus. The share
bus impedance RISHARE should be set as RISET/NCTRL (RISET divided by number of ISL8126 in current
sharing controllers).
There is a 1.2V threshold for average overcurrent protection on this pin. VISHARE is compared with a 1.2V
threshold for average overcurrent protections.
When the fault condition on Channel 1 is detected or EN/VFF1 is pulled below its POR, ISHARE is internally
pulled to VCC.
2
ISET
3
ISHARE
FN7892 Rev.2.00
January 29, 2015
Page 3 of 39
ISL8126
Functional Pin Descriptions
(Continued)
PIN
NUMBER
4, 6
SYMBOL
EN/VFF1, EN/VFF2
DESCRIPTION
These pins have triple functions. The voltage on EN/VFF_ pin is compared with a precision 0.8V threshold
for system enable to initiate soft-start. With a voltage lower than the threshold, the corresponding channel
can be disabled independently. By connecting these pins to the input rail through a voltage resistor divider,
the input voltage can be monitored for UVLO (undervoltage lockout) function. The undervoltage lockout and
its hysteresis levels can be programmed by these resistor dividers. The voltages on these pins are also fed
into the controller to adjust the sawtooth amplitude of each channel independently to realize the
feed-forward function.
Furthermore, during fault (such as overvoltage, overcurrent, and over-temperature) conditions, these pins
(EN/VFF_) are pulled low to communicate the information to other cascaded ICs.
The oscillator switching frequency is adjusted by placing a resistor (RFS) from this pin to GND. The internal
oscillator will lock to an external frequency source if this pin is connected to a switching square pulse
waveform, typically the CLKOUT signal from another ISL8126 or an external clock. The internal oscillator
synchronizes with the leading edge of the input signal.
This pin has a dual function depending on the mode in which the chip is operating. It provides a clock signal
to synchronize with other ISL8126(s) with its VSEN2- pulled within 400mV of VCC for multiphase (3-, 4-, 6-,
8-, 10-, or 12-phase) operation. When the VSEN2- pin is not within 400mV of VCC, ISL8126 is in dual mode
(dual independent PWM output). The clockout signal of this pin is not available in this mode, but the
ISL8126 can be synchronized to external clock. In dual mode, this pin works as the following two functions:
1. An external reference (0.6V target only) can be in place of the Channel 2’s internal reference through
this pin for DDR/tracking applications.
2. The ISL8126 operates as a dual-PWM controller for two independent regulators with selectable phase
degree shift, which is programmed by the voltage level on REFIN (see
“DDR and Dual Mode Operation”
on page 36).
8
PGOOD
Provides an open drain Power-Good signal when both channels are within 9% of the nominal output
regulation point with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs
(VMON1/2) of the internal differential amplifiers.
These pins are the inverting inputs of the error amplifiers. These pins should be connected to VMON1,
VMON2 with the compensation feedback network. No direct connection between FB and VMON pins is
allowed. With VSEN2- pulled within 400mV of VCC, the corresponding error amplifier is disabled and the
amplifier’s output is high impedance. FB2 is one of the two pins to determine the relative phase
relationship between the internal clock of both channels and the CLKOUT signal. See
Table 1
on
page 23.
These pins are outputs of the differential amplifiers. They are connected internally to the OV/UV/PGOOD
comparators. These pins should be connected to the FB1, FB2 pins by a standard feedback network when
both channels are operating independently. When VSEN1-, VSEN2- are pulled within 400mV of VCC, the
corresponding differential amplifier is disabled and its output (VMON pin) is high impedance. In such an
event, the VMON pins can be used as additional monitors of the output voltage with a resistor divider to
protect the system against single point of failure, which occurs in the system using the same resistor
divider for both of the UV/OV comparator and output voltage feedback.
These pins are the negative inputs of standard unity gain operational amplifier for differential remote
sense for the corresponding regulator (Channels 1 and 2), and should be connected to the negative rail of
the load.
When VSEN1-, VSEN2- are pulled within 400mV of VCC, the corresponding error amplifier and differential
amplifier are disabled and their outputs are high impedance. Both VSEN2+ and FB2 input signal levels
determine the relative phases between the internal controllers as well as the CLKOUT signal (see
Table 1
on page 23).
When configured as multiple power modules (each module with independent voltage loop) operating in
parallel, in order to implement the current sharing control, a resistor needs to be inserted between the
VSEN1- pin and the output voltage negative sense point (between VSEN1- and lower voltage sense resistor),
as shown in the “Typical Application Circuits”
“Multiple
Power Modules in Parallel with Current Sharing
Control”
on page 14.
This introduces a correction voltage for the modules with lower load current to keep
the current distribution balanced among modules. The module with the highest load current will
automatically become the master module. The recommended value for the VSEN1- resistor is 100Ω and it
should not be large in order to keep the unit gain amplifier input impedance compatibility. A capacitor is
also recommended to place in parallel with the 100Ω.
5
FSYNC
7
CLKOUT/REFIN
32, 10
FB1, FB2
31, 11
VMON1, VMON2
30, 12
VSEN1-, VSEN2-
FN7892 Rev.2.00
January 29, 2015
Page 4 of 39
ISL8126
Functional Pin Descriptions
(Continued)
PIN
NUMBER
29, 13
SYMBOL
VSEN1+, VSEN2+
DESCRIPTION
These pins are the positive inputs of the standard unity gain operational amplifier for differential remote
sense for the corresponding channel (Channels 1 and 2), and should be connected to the positive rail of the
load. These pins can also provide precision output voltage trimming capability by pulling a resistor from
this pin to the positive rail of the load (trimming down) or the return (typical VSEN1-, VSEN2- pins) of the
load (trimming up). By setting the resistor divider connected from the output voltage to the input of the
differential amplifier, the desired output voltage can be programmed. To minimize the system accuracy
error introduced by the input impedance of the differential amplifier, a resistor below 1kΩ is recommended
to be used for the lower leg (ROS) of the feedback resistor divider.
The typical input impedance of VSEN+ with respect to VSEN- is 500kΩ. With VSEN2- pulled within 400mV
of VCC, the corresponding error amplifier is disabled and VSEN2+ is one of the two pins to determine the
relative phase relationship between the internal clock of both channels and the CLKOUT signal. See
Table 1
on page 23
for details.
These pins are the inverting (-) inputs of the current sensing amplifiers to provide r
DS(ON)
, DCR, or precision
resistor current sensing together with the ISEN1A, ISEN2A pins. Refer to
“2-Phase Operation with rDS(ON)
Sensing” on page 9
for r
DS(ON)
sensing set up and
“2-Phase Operation with DCR Sensing” on page 8
for
DCR sensing set up.
These pins are the non-inverting (+) inputs of the current sensing amplifiers to provide r
DS(ON)
, DCR, or
precision resistor current sensing together with the ISEN1B, ISEN2B pins.
This pin is the input of the internal linear regulator. It should be tied directly to the input rail. The internal
linear device is protected against reverse bias generated by the remaining charge of the decoupling
capacitor at PVCC when losing the input rail. When used with an external 3.3V to 5V supply, this pin can be
tied directly to PVCC to bypass the internal LDO.
These pins provide the bootstrap biases for the high-side drivers. Internal bootstrap diodes connected to
the PVCC pin provide the necessary bootstrap charge. Its typical operational voltage range is 2.5V to 5.6V.
These pins provide the gate signals to drive the high-side devices and should be connected to the MOSFETs’
gates.
Connect these pins to the source of the high-side MOSFETs and the drain of the low-side MOSFETs. These
pins represent the return path for the high-side gate drives.
These pins provide the drive for the low-side devices and should be connected to the MOSFETs’ gates.
This pin is the output of the internal series linear regulator. It provides the bias for both low-side and
high-side drives. Its operational voltage range is 3V to 5.6V. A 10µF ceramic capacitor is required for
decoupling PVCC to ground.
This pin provides bias power for the analog circuitry. An RC filter is recommended between the connection
of this pin to a 3V to 5.6V bias (typically PVCC). R is suggested to be a 5Ω resistor. And in 3.3V applications,
the R could be shorted to allow the low end input in concerns of the VCC falling threshold. The VCC
decoupling capacitor is strongly recommended to be a low ESR ceramic capacitor. This pin can be powered
either by the internal linear regulator or by an external voltage source.
The bottom pad is the signal and power ground plane. All voltage levels are referenced to this pad. This pad
provides a return path for the low-side MOSFET drives and internal power circuitries as well as all analog
signals. Connect this pad to the circuit ground with the shortest possible path (more than 5 to 6 vias to the
internal ground plane, placed on the soldering pad are recommended).
28, 14
ISEN1B, ISEN2B
27, 15
16
ISEN1A, ISEN2A
VIN
25, 17
24, 18
23, 19
22, 20
21
BOOT1, BOOT2
UGATE1, UGATE2
PHASE1, PHASE2
LGATE1, LGATE2
PVCC
26
VCC
EPAD
GND
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
ISL8126CRZ
ISL8126IRZ
ISL8126EVAL1Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for
ISL8126.
For more information on MSL please see techbrief
TB363.
PART MARKING
ISL8126 CRZ
ISL8126 IRZ
Evaluation Board
TEMP RANGE
(°C)
0 to +70
-40 to +85
PACKAGE
(RoHS Compliant)
32 Ld 5x5 QFN
32 Ld 5x5 QFN
PKG.
DWG. #
L32.5x5B
L32.5x5B
FN7892 Rev.2.00
January 29, 2015
Page 5 of 39
FPGA/CPLD
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