OCTAL T1/E1 SHORT HAUL
ANALOG FRONT END
FEATURES
!
IDT82V2048L
!
!
!
!
!
Octal T1/E1 short haul analog front end which supports 100
Ω
T1 twisted pair, 120
Ω
E1 twisted pair and 75
Ω
E1 coaxial
applications
Built-in transmit pre-equalization meets G.703 & T1.102
Digital/Analog LOS detector meets ITU G.775, ETS 300 233 and
T1.231
ITU G.772 non-intrusive monitoring for in-service testing for
any one of channel 1 to channel 7
Low impedance transmit drivers with high-Z
Selectable hardware and parallel/serial host interface
!
!
!
!
!
!
Hitless Protection Switching (HPS) for 1 to 1 protection without
relays
JTAG boundary scan for board test
3.3 V supply with 5 V tolerant I/O
Low power consumption
Operating temperature range: -40
°C
to +85
°C
Available in 144-pin Thin Quad Flat Pack (TQFP) and 160-pin
Plastic Ball Grid Array (PBGA) packages
Green package options available
FUNCTIONAL BLOCK DIAGRAM
LOS
Detector
RTIPn
RRINGn
Peak
Detector
TTIPn
TRINGn
Line
Driver
Waveform
Shaper
Transmit
All Ones
G.772
Monitor
Clock
Generator
Control Interface
Slicer
One of Eight Identical Channels
LOSn
RCn
RDPn
RDNn
TCLKn
TDPn
TDNn
Register
File
JTAG TAP
VDDIO
VDDT
VDDD
VDDA
OE
CLKE
MODE[2:0]
CS
TS2/SCLK/ALE/AS
TS1/RD/R/W
TS0/SDI/WR/DS
SDO/RDY/ACK
INT
D[7:0]/AD[7:0]
MC[3:0]/A[4:0]
MCLK
Figure-1 Block Diagram
TRST
TCK
TMS
TDI
TDO
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
July, 2005
1
DSC-6527/1
2005 Integrated Device Technology, Inc.
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
TDP4
TCLK4
LOS5
RDN5
RDP5
RC5
TDN5
TDP5
TCLK5
TDI
TDO
TCK
TMS
TRST
IC
IC
VDDIO
GNDIO
VDDA
GNDA
MODE0
CS
TS2/SCLK/ALE/AS
TS1/RD/R/W
TS0/SDI/WR/DS
SDO/RDY/ACK
INT
TCLK2
TDP2
TDN2
RC2
RDP2
RDN2
LOS2
TCLK3
TDP3
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TDP7
TCLK7
LOS6
RDN6
RDP6
RC6
TDN6
TDP6
TCLK6
MCLK
MODE2
A4
MC3/A3
MC2/A2
MC1/A1
MC0/A0
VDDIO
GNDIO
VDDD
GNDD
D0/AD0
D1/AD1
D2/AD2
D3/AD3
D4/AD4
D5/AD5
D6/AD6
D7/AD7
TCLK1
TDP1
TDN1
RC1
RDP1
RDN1
LOS1
TCLK0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TDN4
RC4
RDP4
RDN4
LOS4
OE
CLKE
VDDT4
TTIP4
TRING4
GNDT4
RTIP4
RRING4
GNDT5
TRING5
TTIP5
VDDT5
RRING5
RTIP5
VDDT6
TTIP6
TRING6
GNDT6
RTIP6
RRING6
GNDT7
TRING7
TTIP7
VDDT7
RRING7
RTIP7
LOS7
RDN7
RDP7
RC7
TDN7
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
IDT82V2048L
(Top View)
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
TDN3
RC3
RDP3
RDN3
LOS3
RTIP3
RRING3
VDDT3
TTIP3
TRING3
GNDT3
RRING2
RTIP2
GNDT2
TRING2
TTIP2
VDDT2
RTIP1
RRING1
VDDT1
TTIP1
TRING1
GNDT1
RRING0
RTIP0
GNDT0
TRING0
TTIP0
VDDT0
MODE1
LOS0
RDN0
RDP0
RC0
TDN0
TDP0
Figure-2 TQFP144 Package Pin Assignment
2
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
B
TCLK
7
TDP
7
TDN
7
VDDT
7
TTIP
7
C
D
E
F
MC
1
MC
2
MC
3
A4
G
H
J
K
L
TCLK
1
TDP
1
TDN
1
VDDT
1
TTIP
1
M
N
TCLK
0
TDP
0
TDN
0
VDDT
0
TTIP
0
P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RC7
RDP
7
RDN
7
VDDT
7
TRING
7
RC6
RDP
6
RDN
6
VDDT
6
TRING
6
TCLK
MCLK
6
TDP
6
TDN
6
VDDT
6
TTIP
6
MODE
2
LOS
6
LOS
7
VDDIO VDDD
D0
MC
0
D2
D1
D6
D5
D4
D3
D7
MODE
1
LOS
1
LOS
0
RC1
RDP
1
RDN
1
VDDT
1
TRING
1
RC0
RDP
0
RDN
0
VDDT
0
TRING
0
GNDIO GNDD
GNDT GNDT GNDT GNDT
7
7
6
6
RTIP
7
RTIP
4
RRING
7
RRING
4
RTIP
6
RTIP
5
RRING
6
RRING
5
GNDT GNDT GNDT GNDT
1
1
0
0
IDT82V2048L
(Bottom View)
RRING
1
RRING
2
RTIP
1
RTIP
2
RRING
0
RRING
3
RTIP
0
RTIP
3
GNDT GNDT GNDT GNDT
4
4
5
5
TRING
4
VDDT
4
RDN
4
RDP
4
RC4
A
TTIP
4
VDDT
4
TDN
4
TDP
4
TCLK
4
B
TRING
5
VDDT
5
RDN
5
RDP
5
RC5
C
TTIP
5
VDDT
5
TDN
5
TDP
5
TCLK
5
D
LOS
4
LOS
5
CLKE
OE
E
TMS
TDI
TDO
TCK
F
GNDIO GNDA
TRST
IC
MODE
0
IC
CS
TS
2
TS
1
TS
0
J
LOS
3
LOS
2
INT
SDO
K
GNDT GNDT GNDT GNDT
2
2
3
3
TTIP
2
VDDT
2
TDN
2
TDP
2
TCLK
2
L
TRING
2
VDDT
2
RDN
2
RDP
2
RC2
M
TTIP
3
VDDT
3
TDN
3
TDP
3
TCLK
3
N
TRING
3
VDDT
3
RDN
3
RDP
3
RC3
P
VDDIO VDDA
G
H
Figure-3 PBGA160 Package Pin Assignment
3
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
1
PIN DESCRIPTION
Table-1 Pin Description
Name
Type
Pin No.
TQFP144
PBGA160
Transmit and Receive Line Interface
TTIP0
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
TRING0
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
RTIP0
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
RRING0
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
45
52
57
64
117
124
129
136
46
51
58
63
118
123
130
135
48
55
60
67
120
127
132
139
49
54
61
66
121
126
133
138
N5
L5
L10
N10
B10
D10
D5
B5
P5
M5
M10
P10
A10
C10
C5
A5
P7
M7
M8
P8
A8
C8
C7
A7
N7
L7
L8
N8
B8
D8
D7
B7
Description
Analog
Output
TTIPn/TRINGn: Transmit Bipolar Tip/Ring for Channel 0~7
These pins are the differential line driver outputs. They will be in high impedance state if pin OE is low or
the corresponding pin TCLKn is low (pin OE is global control, while pin TCLKn is per-channel control). In
host mode, each pin can be in high impedance by programming a ‘1’ to the corresponding bit in register
OE
(1)
.
Analog
Input
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 0~7
These pins are the differential line receiver inputs.
1
. Register name is indicated by bold capital letter. For example,
OE
indicates Output Enable Register.
4
IDT82V2048L OCTAL T1/E1 SHORT HAUL ANALOG FRONT END
INDUSTRIAL TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
Type
Pin No.
TQFP144
PBGA160
Description
Transmit and Receive Digital Data Interface
TDP0
TDP1
TDP2
TDP3
TDP4
TDP5
TDP6
TDP7
I
TDN0
TDN1
TDN2
TDN3
TDN4
TDN5
TDN6
TDN7
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
RDP0
RDP1
RDP2
RDP3
RDP4
RDP5
RDP6
RDP7
RDN0
RDN1
RDN2
RDN3
RDN4
RDN5
RDN6
RDN7
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
38
31
79
72
109
102
7
144
36
29
81
74
107
100
9
2
40
33
77
70
111
104
5
142
41
34
76
69
112
105
4
141
39
32
78
71
110
103
6
143
N3
L3
L12
N12
B12
D12
D3
B3
N1
L1
L14
N14
B14
D14
D1
B1
P2
M2
M13
P13
A13
C13
C2
A2
P3
M3
M12
P12
A12
C12
C3
A3
P1
M1
M14
P14
A14
C14
C1
A1
37
30
80
73
108
101
8
1
N2
L2
L13
N13
B13
D13
D2
B2
TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
The NRZ data to be transmitted for positive/negative pulse is input on this pin. Data on TDPn/TDNn are
active high and are sampled on the falling edges of TCLKn.
TDPn
0
0
1
1
TDNn
0
1
0
1
Output Pulse
Space
Negative Pulse
Positive Pulse
Space
I
TCLKn: Transmit Clock for Channel 0~7
The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The
transmit data at TDPn or TDNn is sampled into the device on the falling edges of TCLKn.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as
Table-2
System Interface Configuration.
O
High
Imped-
ance
RDPn/RDNn: Positive/Negative Receive Data for Channel 0~7
These pins output the raw RZ sliced data. The active polarity of RDPn/RDNn is determined by pin CLKE.
When pin CLKE is low, RDPn/RDNn is active low. When pin CLKE is high, RPDn/RDNn is active high.
RDPn/RDNn will remain active during LOS. RDPn/RDNn is set into high impedance when the correspond-
ing receiver is powered down.
O
High
Imped-
ance
RCn: Receive Pulse for Channel 0~7
RCn is the output of an internal exclusive OR (XOR) which is connected with RDPn and RDNn. The clock
is recovered from the signal on RCn. If receiver n is powered down, the corresponding RCn will be in high
impedance.
5
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