DATASHEET
ISL78229
2-Phase Boost Controller with Drivers and I
2
C/PMBus
The
ISL78229
is an automotive grade (AEC-Q100 Grade 1),
2-phase 55V synchronous boost controller that simplifies the
design of high power boost applications. It integrates strong
half-bridge drivers, an analog/digital tracking input,
comprehensive protection functions, and a PMBus interface for
added control and telemetry.
The ISL78229 enables a simple, modular design for systems
requiring power and thermal scalability. It offers peak-current
mode control for fast line response and simple compensation.
Its synchronous 2-phase architecture enables it to support
higher current while reducing the size of input and output
capacitors. The integrated drivers feature programmable
adaptive dead time control, offering flexibility in power stage
design. The ISL78229 offers a 90° output clock and supports
1-, 2-, and 4-phases.
The ISL78229 offers a highly robust solution for the most
demanding environments. Its unique soft-start control prevents
large negative current even in extreme cases, such as a restart
under high output pre-bias on high volume capacitances. It also
offers two levels of cycle-by-cycle OCP, average current limiting,
input OVP, output UVP/OVP, and internal OTP. A thermistor input
provides external OTP for the power-stage elements. In the event
of a fault, the ISL78229 offers individually programmable
latch-off or hiccup recovery for each fault type.
Also integrated are several functions that ease system design. A
unique tracking input controls the output voltage, allowing it to
track either a digital duty cycle (PWM) signal or an analog
reference. The ISL78229 provides input average current limiting
so the system can deliver transient bursts of high load current
while limiting the average current to avoid overheating. The
ISL78229 PMBus interface provides fault reporting, telemetry,
and system control to support functional safety qualification.
FN8656
Rev.5.00
Sep 18, 2017
Features
• Input/output voltage range: 5V to 55V, withstands 60V
transients
• Supports synchronous or standard boost topology
• Peak current mode control with adjustable slope
compensation
• Secondary average current control loop
• Integrated 5V 2A sourcing/3A sinking N-channel MOSFET
drivers
• Switching frequency: 50kHz to 1.1MHz per phase
• External synchronization
• Programmable minimum duty cycle
• Programmable adaptive dead time control
• Optional diode emulation and phase dropping
• PWM and analog track function
• Forced PWM operation with negative current limiting and
protection
• Comprehensive protection/fault reporting
• Selectable hiccup or latch-off fault response
• I
2
C/PMBus compatible digital interface
•
AEC-Q100
qualified, Grade 1: -40°C to +125°C
• 6mm x 6mm 40 Ld WFQFN (Wettable Flank QFN) package
Applications
• Automotive power systems (for example, 12V to 24V, 12V to
48V, etc.)
- Trunk audio amplifiers
- Start-stop systems
- Automotive boost applications
• Industrial and telecommunication power supplies
Related Literature
• For a full list of related documents, visit our website
-
ISL78229
product page
PVCC
VIN
VIN
EN
VOUT
BOOT1
UG1
NTC
PH1
LG1
PMBus
SDA
SCL
SALERT
ISL78229
POWER-GOOD
PGOOD
BOOT2
UG2
PH2
CLOCK_OUT
CLKOUT
LG2
SS
ISEN2N
COMP
ISEN2P
FB
R
SEN2
ISEN1N
ISEN1P
R
SEN1
VIN
100
95
90
85
80
75
70
65
60
55
50
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
LOAD CURRENT (A)
V
O
= 36V
EN_IC
EFFICIENCY (%)
V
O
= 18V
V
O
= 24V
TRACK
NOTE: (See Typical Application in
Figure 4 on page 8.)
FIGURE 1. SIMPLIFIED APPLICATION SCHEMATIC, 2-PHASE
SYNCHRONOUS BOOST
FIGURE 2. EFFICIENCY CURVES, V
IN
= 12V, T
A
= +25°C
FN8656 Rev.5.00
Sep 18, 2017
Page 1 of 73
ISL78229
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Application - 2-Phase Synchronous Boost . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 9
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operation Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Synchronous Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Multiphase Power Conversion . . . . . . . . . . . . . . . . . . . . . . . . . 27
Oscillator and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . 29
Operation Initialization and Soft-Start. . . . . . . . . . . . . . . . . . . 30
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PGOOD Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Current Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Adjustable Slope Compensation . . . . . . . . . . . . . . . . . . . . . . . 33
Light-Load Efficiency Enhancement . . . . . . . . . . . . . . . . . . . . 34
Fault Protections/Indications. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Internal 5.2V LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PMBus User Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Monitor Operating Parameters via PMBus. . . . . . . . . . . . . . . 40
Monitor Faults and Configure Fault Responses . . . . . . . . . . . 41
Set Operation/Fault Thresholds via PMBus . . . . . . . . . . . . . . 41
Accessible Timing for PMBus Registers Status . . . . . . . . . . . 41
Device Identification Address and Read/Write . . . . . . . . . . . 43
PMBus Data Formats Used in ISL78229 . . . . . . . . . . . . . . . . 43
PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . .44
PMBus Command Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
OPERATION (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
CLEAR_FAULTS (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
WRITE_PROTECT (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
CAPABILITY (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
VOUT_COMMAND (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
VOUT_TRANSITION_RATE (27h) . . . . . . . . . . . . . . . . . . . . . . . . 50
OT_NTC_FAULT_LIMIT (4Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
OT_NTC_WARN_LIMIT (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . 52
READ_VIN (88h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
READ_VOUT (89h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
READ_IIN (8Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
READ_TEMPERATURE (8Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PMBUS_REVISION (98h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
IC_DEVICE_ID (ADh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
IC_DEVICE_REV (AEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
FAULT_STATUS (D0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
FAULT_MASK (D1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SET_FAULT_RESPONSE (D2h) . . . . . . . . . . . . . . . . . . . . . . . . . 61
VOUT_OV_FAULT_LIMIT (D3h) . . . . . . . . . . . . . . . . . . . . . . . . . 62
VOUT_UV_FAULT_LIMIT (D4h) . . . . . . . . . . . . . . . . . . . . . . . . . 63
CC_LIMIT (D5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
OC_AVG_FAULT_LIMIT (D6h) . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Output Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration to Support Single Phase Boost. . . . . . . . . . . .
66
66
66
67
67
67
67
69
69
69
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
About Intersil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
FN8656 Rev.5.00
Sep 18, 2017
Page 2 of 73
ISL78229
Pin Configuration
ISL78229
(40 LD 6x6 WFQFN)
TOP VIEW
ATRK/DTRK
HIC/LATCH
ISEN2N
ISEN1N
32
ISEN2P
ISEN1P
VCC
RDT
40
SLOPE
FB
COMP
SS
IMON
TRACK
ADDR1
ADDR2
PGOOD
FSYNC
1
2
3
4
5
6
7
8
9
10
11
SGND
39
38
37
36
35
34
33
VIN
31
30 BOOT1
29 UG1
28 PH1
27 LG1
26 PVCC
25 PGND
24 LG2
23 PH2
22 UG2
21 BOOT2
20
CLKOUT
12
SDA
13
SCL
14
SALERT
NC
15
NTC
PAD
16
DE/PHDRP
17
RBLANK
18
PLLCOMP
19
EN
Functional Pin Description
PIN NAME
SLOPE
FB
PIN #
1
2
DESCRIPTION
Programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE pin to GND. Refer
to
“Adjustable Slope Compensation” on page 33
for information about how to select this resistor value.
The inverting input of the error amplifier for the voltage regulation loop. A resistor network must be placed between the
FB pin and the output rail to set the boost converter’s output voltage. Refer to
“Output Voltage Setting” on page 66
for more
details.
This pin also has output overvoltage and undervoltage comparators. Refer to
“Output Undervoltage Fault” on page 36
and
“Output Overvoltage Fault” on page 36
for more details.
The output of the transconductance error amplifier (Gm1) for the output voltage regulation loop. Place the compensation
network between the COMP pin and ground. Refer to
“Output Voltage Regulation Loop” on page 26
for more details.
The COMP pin voltage can also be controlled by the constant current control loop error amplifier (Gm2) output through
a diode (
D
CC)
when the constant current control loop is used to control the input average current. Refer to
“Constant
Current Control (CC)” on page 37
for more details.
A capacitor placed from SS to ground sets up the soft-start ramp rate and in turn, determines the soft-start time. Refer
to
“Soft-Start” on page 31
for more details.
COMP
3
SS
4
FN8656 Rev.5.00
Sep 18, 2017
Page 3 of 73
ISL78229
Functional Pin Description
(Continued)
PIN NAME
IMON
PIN #
5
DESCRIPTION
The average current monitor pin for the sum of the two phases’ inductor currents. It is used for average current limiting and
average current protection functions.
The sourcing current from the IMON pin is the sum of the two CSA’s outputs plus a fixed 17µA offset current. With each CSA
sensing individual phase’s inductor current, the IMON signal represents the sum of the two phases’ inductor currents and is
the input current for the boost. Place a resistor in parallel with a capacitor from IMON to ground. The IMON pin output current
signal builds up the average voltage signal representing the average current sense signals.
A constant average current limiting function and an average current protection are implemented based on the IMON signal.
1. Constant Average Current Limiting: A Constant Current (CC) control loop is implemented to limit the IMON average
current signal using a 1.6V reference, which ultimately limits the total input average current to a constant level.
2. Average Current Protection: If the IMON pin voltage is higher than 2V, the part will go into either Hiccup or Latch-off fault
protection as described in
“Fault Response Register SET_FAULT_RESPONSE (D2h)” on page 35.
Refer to
“Average Current Sense for 2 Phases - IMON” on page 33
for more details.
TRACK
6
External reference input pin for the IC output voltage regulation loop to follow. The input reference signal can be either a digital
or analog signal selected by the ATRK/DTRK pin configuration.
If the TRACK function is not used, connect the TRACK pin to VCC and the internal VREF_DAC will work as the reference. Refer
to
“Digital/Analog TRACK Function” on page 26
for more details.
ADDR1, a logic input in combination with ADDR2, selects one of four bus addresses. Refer to
“Device Identification
Address and Read/Write” on page 43
for more details.
ADDR2, a logic input in combination with ADDR1, selects one of four bus addresses. Refer to
“Device Identification
Address and Read/Write” on page 43
for more details.
Provides an open-drain power-good signal. Pull up this pin with a resistor to this IC’s VCC for proper function. When the output
voltage is within OV/UV thresholds and soft-start is completed, the internal PGOOD open-drain transistor is open and PGOOD
is pulled HIGH. It will be pulled low once output UV/OV or input OV conditions are detected. Refer to
“PGOOD Signal” on
page 31
for more details.
A dual-function pin for switching frequency setting and synchronization defined as follows:
1. The PWM switching frequency can be programmed by a resistor R
FSYNC
from this pin to ground. The PWM frequency
refers to a single-phase switching frequency in this datasheet. The typical programmable frequency range is 50kHz
to 1.1MHz.
2. The PWM switching frequency can also be synchronized to an external clock applied on the FSYNC pin. The FSYNC
pin detects the input clock signal’s rising edge to be synchronized with. The typical detectable minimum pulse width
of the input clock is 20ns. The rising edge of LG1 is delayed by 35ns from the rising edge of the input clock signal
at the FSYNC pin. Once the internal clock is locked to the external clock, it will latch to the external clock. If the
external clock on the FSYNC pin is removed, the switching frequency oscillator will shut down. The part will then
detect PLL_LOCK fault and go to either Hiccup mode or Latch-off mode as described in
“Fault Response Register
SET_FAULT_RESPONSE (D2h)” on page 35.
If the part is set in Hiccup mode, the part will restart with the frequency
set by R
FSYNC
.
SGND
11
Signal ground pin that the internal sensitive analog circuits refer to. Connect this pin to a large copper ground plane free
from large noisy signals. In layout power flow planning, avoid having the noisy high frequency pulse current flowing
through the ground area around the IC.
Serial bus data input/output. Requires pull-up.
Serial bus clock input. Requires pull-up.
PMBus Alert Output. An open-drain output that is pulled low when a fault condition is detected. Requires pull-up. Refer to
“Fault
Flag Register FAULT_STATUS (D0h) and SALERT Signal” on page 35
for more details.
External temperature sensor input. An NTC resistor from this pin to GND can be used as the external temperature sensing
component. A 20µA current sources out of this pin. The voltage at this pin is 20µA times the NTC resistor, which
represents the temperature. The voltage on this pin is converted by the internal ADC and stored in the NTC register which
can be read over the PMBus. Refer to
“External Temperature Monitoring and Protection (NTC Pin)” on page 38
for more
details.
Used to select Diode Emulation mode (DE), Phase Dropping (PH_DROP) mode, or Continuous Conduction Mode (CCM). There
are 3 configurable modes: 1. DE mode; 2. DE plus PH_DROP mode; 3. CCM mode.
Refer to
Table 2 on page 34
for the three configurable options.
The phase dropping mode is not allowed with external synchronization.
A resistor from this pin to ground programs the blanking time for current sensing after the PWM is ON (LG is ON). This
blanking time is also called t
MINON
time, meaning the minimum ON-time once a PWM pulse is ON. Refer to
“Minimum
On-Time (Blank Time) Consideration” on page 30
for information about R
BLANK
.
ADDR1
ADDR2
PGOOD
7
8
9
FSYNC
10
SDA
SCL
SALERT
NTC
12
13
14
15
DE/PHDRP
16
RBLANK
17
FN8656 Rev.5.00
Sep 18, 2017
Page 4 of 73
ISL78229
Functional Pin Description
(Continued)
PIN NAME
PLLCOMP
PIN #
18
DESCRIPTION
The compensation node for the switching frequency clock’s Phase Lock Loop (PLL). A second order passive loop filter
connected between this pin and ground compensates the PLL. Refer to
“Oscillator and Synchronization” on page 29
for more
details.
A threshold-sensitive enable input for the controller. When the EN pin is driven above 1.2V, the ISL78229 is enabled and
the internal LDO is activated to power up PVCC followed by a start-up procedure. Driving the EN pin below 0.95V will
disable the IC and clear all fault states. Refer to
“Enable” on page 31
for more details.
Outputs a clock signal with same frequency to one phase’s switching frequency. The rising edge signal on the CLKOUT pin is
delayed by 90° from the rising edge of LG1 of the same IC. With CLKOUT connected to the FSYNC pin of the second ISL78229,
a 4-phase interleaving operation can be achieved. Refer to
“Oscillator and Synchronization” on page 29
for more details.
Provides bias voltage to the Phase 2 high-side MOSFET driver. A bootstrap circuit creates a voltage suitable to drive the external
N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between the BOOT2 and PH2
pins. In the typical configuration, PVCC provides the bias to BOOT2 through a fast switching diode.
In applications in which a high-side driver is not needed (for example, a standard boost application), BOOT2 is
recommended to be connected to ground. The ISL78229 IC can detect BOOT2 being grounded during start-up and both
the Phase 1 and Phase 2 high-side drivers will be disabled. In addition, PH1 and PH2 should also be tied to ground.
Phase 2 high-side gate driver output. Disable this output by tying either BOOT1 and PH1 to ground or BOOT2 and PH2 to
ground.
This pin represents the return path for the Phase 2 high-side gate drive. Connect this pin to the source of the Phase 2
high-side MOSFETs and the drain of the low-side MOSFETs.
Phase 2 low-side gate driver output. It should be connected to the Phase 2 low-side MOSFETs’ gates.
Provides the return path for the low-side MOSFET drivers. This pin carries a noisy driving current, so the traces connecting
from this pin to the low-side MOSFET source and PVCC decoupling capacitor ground pad should be as short as possible.
All the sensitive analog signal traces should not share common traces with this driver return path. Connect this pin to
the ground copper plane (wiring away from the IC instead of connecting through the IC bottom PAD) through several vias
as close as possible to the IC.
Output of the internal linear regulator that provides bias for the low-side driver, high-side driver (PVCC connected to BOOTx
through diodes) and VCC bias (PVCC and VCC are typically connected through a small resistor like 10Ω or smaller, which helps
to filter out the noises from PVCC to VCC). The PVCC operating range is 4.75V to 5.5V. A minimum 10µF decoupling ceramic
capacitor should be used between PVCC and PGND. Refer to
“Internal 5.2V LDO” on page 39
for more details.
Phase 1 low-side gate driver output. It should be connected to the Phase 1 low-side MOSFETs’ gates.
Connect this pin to the source of the Phase 1 high-side MOSFETs and the drain of the low-side MOSFETs. This pin
represents the return path for the Phase 1 high-side gate drive.
Phase 1 high-side MOSFET gate drive output. Disable this output by tying either BOOT1 and PH1 to ground or BOOT2 and
PH2 to ground.
Provides bias voltage to the Phase 1 high-side MOSFET driver. A bootstrap circuit creates a voltage suitable to drive the external
N-channel MOSFET. A 0.47µF ceramic capacitor in series with a 1.5Ω resistor are recommended between BOOT1 and PH1
pins. In a typical configuration, PVCC provides the bias to BOOT1 through a fast switching diode.
In applications in which a high-side driver is not needed (for example, standard boost application), the BOOT1 is
recommended to be connected to ground. The ISL78229 IC can detect BOOT1 being grounded during start-up and both
the Phase 1 and Phase 2 high-side drivers will be disabled. In addition, PH1 and PH2 should also be tied to ground.
Connect the supply rail to this pin. Typically, connect the boost input voltage to this pin. The VIN pin can also be supplied by a
separate input source independent from the boost power stage input source. This pin is connected to the input of the internal
linear regulator, generating the power necessary to operate the chip. The DC voltage applied to the VIN should not exceed 55V
during normal operation. VIN can withstand transients up to 60V, but in this case, the device's overvoltage protection will stop
it from switching to protect itself. Refer to
“Input Overvoltage Fault” on page 36
for more details.
The negative potential input to the Phase 1 current sense amplifier. This amplifier continuously senses the Phase 1
inductor current through a power current sense resistor in series with the inductor. The sensed current signal is used for
current mode control, peak current limiting, average current limiting, and diode emulation.
The positive potential input to the Phase 1 current sense amplifier.
The negative potential input to the Phase 2 current sense amplifier. This amplifier continuously senses the Phase 2
inductor current through a power current sense resistor in series with the inductor. The sensed current signal is used for
current mode control, peak current limiting, average current limiting, and diode emulation.
The positive phase input to the Phase 2 current sense amplifier.
Not connected. This pin is not electrically connected internally.
EN
19
CLKOUT
20
BOOT2
21
UG2
PH2
LG2
PGND
22
23
24
25
PVCC
26
LG1
PH1
UG1
BOOT1
27
28
29
30
VIN
31
ISEN1N
32
ISEN1P
ISEN2N
33
34
ISEN2P
NC
35
36
FN8656 Rev.5.00
Sep 18, 2017
Page 5 of 73
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