• Phase-Lock Loop Clock Distribution for Synchronous DRAM
Applications
• Distributes one clock input to one bank of ten outputs
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the output
to the clock input signal
• On-chip series damping resistors with each driver
• No external RC network required for PLL loop stability
• Operates at 3.3V V
DD
• tpd Phase Error at 133MHz: < ±150ps
• Jitter (cycle-cycle)(peak-to-peak) at 66MHz to 133MHz: | 70 | ps
• Spread Spectrum Compatible
• Operating frequency 25MHz to 140MHz
• Fully conforms to PC133 specifications
• Available in 24-Pin TSSOP package
DESCRIPTION:
The IDTCSPF2510C is a high performance, low-skew, low-jitter,
phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both
frequency and phase, the feedback (FBOUT) output to the clock (CLK) input
signal. It is specifically designed for use with synchronous DRAMs. The
CSPF2510C operates at 3.3V and provides integrated series-damping
resistors that make it ideal for driving point-to-point loads, single or dual.
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50 percent, independent of the duty cycle
at CLK. The outputs can be enabled or disabled via the control G input. When
the G input is high, the outputs switch in phase and frequency with CLK; when
the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CSPF2510C does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CSPF2510C requires a
stabilization time to achieve phase lock of the feedback signal to the reference
signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any
changes to the PLL reference or feedback signals. The PLL can be
bypassed for the test purposes by strapping AV
DD
to ground.
The CSPF2510C is characterized for operation from 0°C to +85°C. This
device is also available (on special order) in Industrial (-40°C to +85°C)
temperatures. See Ordering Information for more details.
FUNCTIONAL BLOCK DIAGRAM
11
G
3
Y0
4
Y1
5
Y2
8
Y3
9
Y4
15
Y5
16
Y6
17
CLK
24
PLL
13
FBIN
21
AV
DD
23
12
FBOUT
Y9
20
Y8
Y7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
0ºC TO 85ºC TEMPERATURE RANGE
º
º
1
c
2002
Integrated Device Technology, Inc.
AUGUST 2002
DSC-5409/6
IDTCSPF2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0ºC TO 85ºC TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DD
Rating
Supply Voltage Range
Input Voltage Range
Voltage range applied to any
output in the high or low state
Input clamp current
Terminal Voltage with Respect
to GND (inputs V
IH
2.5, V
IL
2.5)
Continuous Output Current
Continuous Current
Storage Temperature Range
Junction Temperature
±50
±100
– 65 to +150
+150
mA
mA
°C
°C
Max
–0.5 to +4.6
–0.5 to +6.5
–0.5 to V
DD
+ 0.5
–50
±50
Unit
V
V
V
mA
mA
AGND
V
DD
Y0
Y1
Y2
GND
GND
Y3
Y4
V
DD
G
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AV
DD
V
DD
Y9
Y8
GND
GND
Y7
Y6
Y5
V
DD
FBIN
V
I(1)
V
O(1,2)
I
IK
(V
I
<0)
I
OK
(V
O
<0 or
V
O
> V
DD
)
I
O
(V
O
= 0 to V
DD
)
V
DD
or GND
T
STG
T
J
TSSOP
TOP VIEW
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150
°
C and a board trace length of 750 mils.
CAPACITANCE
Parameter
Description
Input Capacitance
V
I
= V
DD
or GND
C
O
C
L
Output Capacitance
V
C
= V
DD
or GND
Load Capacitance
Min.
Typ.
5
6
25
Max.
Unit
pF
pF
pF
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
C
IN
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
, AV
DD
T
A
Power Supply Voltage
Operating Free-Air Temperature
Description
Min.
3
0
Max.
3.6
+85
Unit
V
°
C
2
IDTCSPF2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0ºC TO 85ºC TEMPERATURE RANGE
PIN DESCRIPTION
Terminal
Name
CLK
No.
24
Type
I
Description
Clock input. CLK provides the clock signal to be distributed by the CSPF2510C clock driver. CLK is used to provide the reference
signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain
phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock
the feedback signal to its reference signal.
FBIN
G
FBOUT
Y (0:9)
13
11
12
3, 4, 5, 8, 9,
15, 16, 17,
20, 21
AV
DD
AGND
V
DD
GND
23
1
Power
Ground
Analog power supply. AV
DD
provides the power reference for the analog circuitry. In addition, AV
DD
can be used to bypass the PLL
for test purposes. When AV
DD
is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply
Ground
2, 10, 14, 22 Power
6, 7, 18, 19 Ground
I
I
O
O
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The
integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs Y(0:9). When G is low, outputs Y(0:9) are disabled to a logic-low state. When
G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25Ω series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank Y(0:9) is enabled via the G input. These outputs can be
disabled to a logic-low state by de-asserting the G control input. Each output has an integrated 25Ω series-damping resistor.
STATIC FUNCTION TABLE
(AV
DD
= 0V)
Inputs
G
L
L
H
H
H
CLK
L
H
H
L
running
Y (0:9)
L
L
H
L
running
Outputs
FBOUT
L
H
H
L
running
DYNAMIC FUNCTION TABLE
(AV
DD
= 3.3V)
Inputs
G
X
L
L
H
H
CLK
L
running
H
running
H
Y (0:9)
L
L
L
running in
phase with CLK
H
Outputs
FBOUT
L
running in
phase with CLK
H
running in
phase with CLK
H
3
IDTCSPF2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0ºC TO 85ºC TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERA-
TURE RANGE (UNLESS OTHERWISE NOTED)
Symbol
V
IH
V
IL
V
IK
V
OH
Test Conditions
Input HIGH Level
Input LOW Level
I
I
= -18mA
I
OH
= -100µA
I
OH
= -12mA
I
OH
= -6mA
I
OL
= 100µA
V
OH
I
I
I
DD
∆I
DD
C
PD
I
DDA
(2)
V
DD
3V
Min. to Max.
3V
3V
Min. to Max.
3V
3V
3.6V
3.6V
3.3V to 3.6V
3.6V
AV
DD
= 3.3V
Min.
2
V
DD
– 0.2
2.1
2.4
Typ.
10
10
Max.
0.8
– 1.2
0.2
0.8
0.55
±5
10
500
14
Unit
V
V
V
V
I
OL
= 12mA
I
OL
= 6mA
V
I
= V
DD
or GND
V
I
= V
DD
or GND, AV
DD
= GND, I
O
= 0, Outputs: LOW or HIGH
One input at V
DD
- 0.6V, other inputs at V
DD
or GND
Power Dissipation Capacitance
AV
DD
Power Supply Current
V
µA
µA
µA
pF
mA
NOTES:
1. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions.
2. For I
DD
of AV
DD
, see TYPICAL CHARACTERISTICS.
TIMING REQUIREMENTS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND
OPERATING FREE-AIR TEMPERATURE
Min.
Clock frequency
f
CLOCK
Input clock duty cycle
Stabilization time
(1)
25
40%
Max.
140
60%
1
ms
Unit
MHz
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase
reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics
table are not applicable.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C
L
= 25pF
V
DD
= 3.3V ± 0.165V
Parameter
(1)
t
PHASE
error
(2)
t
PHASE
error – jitter
(2,4)
t
SK(o)
(3)
Jitter (cycle-cycle)
(peak-to-peak)
Duty cycle reference
(5)
t
R
t
F
From (Input)
100MHz < CLK↑ < 133MHz
CLK↑ = 133MHz
Any Y (133MHz)
CLK = 66MHz to 133MHz
CLK = 100MHz to 133MHz
CLK = 133MHz
To (Output)
FBIN↑
FBIN↑
Any Y
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Min.
Typ.
Max.
Min.
– 150
V
DD
= 3.3V ± 0.3V
Typ.
Max.
150
Unit
ps
ps
ps
ps
ps
%
ns
ns
– 50
1.3
1.7
50
1.9
2.5
45
0.8
0.8
|
70
|
|
65
|
150
55
2.1
2.5
NOTES:
1. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
2. See PARAMETER MEASUREMENT INFORMATION.
3. The t
SK(O)
specification is only valid for equal loading of all outputs.
4. Phase error does not include jitter.
5. See TYPICAL CHARACTERISTICS.
4
IDTCSPF2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0ºC TO 85ºC TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION
(2)
From Output
Under Test
3V
See Note 5
Input
t
PHA SE ER R OR
C
L
= 25pF
(1)
0V
2V
0.4V
t
R
V
OH
2V
0.4V
V
OL
500
Ω
Output
or
FBIN
See Note 5
t
F
Load Circuit Waveforms
Load Voltage Waveforms
Propagation Delay Times
PHASE ERROR AND SKEW CALCULATIONS
(3,4,5)
CLK
FBIN
t
PHASE
ERRO R
CLK
Y
C
L
= 25pF
(1)
CSPF2510C
F
BOU T
500
Ω
on each
Y output
FBOUT
F
BIN
C
F
Any Y
t
SK(o)
PCB
TR AC E
Any Y
Any Y
t
SK(o)
NOTES:
1. C
L
includes probe and jig capacitance.
2. All inputs pulses are supplied by generators having the following characteristics: P
RR
≤
100MHz, Z
O
= 50Ω, t
R
≤
1.2 ns, t
F
≤
1.2 ns.
3. The outputs are measured one at a time with one transition per measurement.
4. Phase error measurements require equal loading at outputs Y and F
BOUT
. C
F
= C
L
– C
FBIN
– C
PCB
TRACE
; C
FBIN
≅
6
pF
.
5. V threshold set at 1.5V across Voltage/Temp operating range.
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