18Mb Pipelined
DDR™II SRAM
Burst of 2
Features
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IDT71P71804
IDT71P71604
Description
The IDT DDRII
TM
Burst of two SRAMs are high-speed synchro-
nous memories with a double-data-rate (DDR), bidirectional data port.
This scheme allows maximization of the bandwidth on the data bus by
passing two data items per clock cycle. The address bus operates at
single data rate speeds, allowing the user to fan out addresses and
ease system design while maintaining maximum performance on data
transfers.
The DDRII has scalable output impedance on its data output bus
and echo clocks, allowing the user to tune the bus for low noise and high
performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds
beyond SRAM devices that use any form of TTL interface. The inter-
face can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a V
DDQ
and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V V
DD.
The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
Clocking
The DDRII SRAM has two sets of input clocks, namely the K,
K
clocks and the C,
C
clocks. In addition, the DDRII has an output “echo”
clock, CQ,
CQ.
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18Mb Density (1Mx18, 512kx36)
Common Read and Write Data Port
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
Multiplexed Address Bus
-
One Read or One Write request per clock cycle
DDR (Double Data Rate) Data Bus
- Two word bursts data per clock
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals from
1.4V to 1.9V.
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
-
Output Impedance adjustable from 35 ohms to 70
ohms
1.8V Core Voltage (V
DD
)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
Functional Block Diagram
DATA
REG
(Note 1)
WRITE DRIVER
OUTPUT SELECT
SENSE AMPS
LD
R/
W
BW
x
(Note3)
CTRL
LOGIC
18M
MEMORY
ARRAY
(Note1)
OUTPUT REG
SA
SA
0
ADD
REG
(Note2)
WRITE/READ DECODE
(Note2)
(Note4)
(Note1)
DQ
K
K
C
C
CLK
GEN
SELECT OUTPUT CONTROL
6112 drw 16
CQ
CQ
Notes
1) Represents 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x18 and 19 address signal lines for x36.
3) Represents 2 signal lines for x18 and 4 signal lines for x36.
4) Represents 36 signal lines for x18 and 72 signal lines for x36.
1
APRIL 2006
DSC-6112/0A
©2006 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
The K and
K
clocks are the primary device input clocks. The K clock
is used to clock in the control signals (LD, R/W and
B Wx),
the address,
and the first word of the data burst during a write operation. The
K
clock
is used to clock in the control signals (B
Wx),
and the second word of the
data burst during a write operation. The K and
K
clocks are also used
internally by the SRAM. In the event that the user disables the C and
C
clocks, the K and
K
clocks will also be used to clock the data out of the
output register and generate the echo clocks.
The C and
C
clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C
must be presented to the SRAM within the timing tolerances. The
output data from the DDRII will be closely aligned to the C and
C
input,
through the use of an internal DLL. When C is presented to the DDRII
SRAM, the DLL will have already internally clocked the first data word to
arrive at the device output simultaneously with the arrival of the
C
clock.
The C and second data word of the burst will also correspond.
Single Clock Mode
The DDRII SRAM may be operated with a single clock pair. C and
C
may be disabled by tying both signals high, forcing the outputs and echo
clocks to be controlled instead by the K and
K
clocks.
DLL Operation
The DLL in the output structure of the DDRII SRAM can be used to
closely align the incoming clocks C and
C
with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding
Df
low. With the DLL off, the C and
C
(or K and
K
of
if C and
C
are not used) will directly clock the output register of the SRAM.
With the DLL off, there will be a propagation delay from the time the clock
enters the device until the data appears at the output.
Echo Clock
The echo clocks, CQ and
CQ,
are generated by the C and
C
clocks
(or K,
K
if C,
C
are disabled). The rising edge of C generates the rising
edge of CQ, and the falling edge of
CQ.
The rising edge of
C
generates
the rising edge of
CQ
and the falling edge of CQ. This scheme improves
the correlation of the rising and falling edges of the echo clock and will
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
Read operations are initiated by holding Read/Write control input
(R/W ) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
output at the designated time in correspondence with the C and
C
clocks.
Write operations are initiated by holding the Read/Write control input
(R/W ) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
the address. On the following rising edge of K, the first word of the two
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write (BWx) inputs. On the following rising edge of
K,
the second half of the data write burst will be accepted at the device input
with the designated (BWx) inputs.
DDRII devices internally store two words of the burst as a single,
wide word and will retain their order in the burst. The x18 and x36 DDRll
devices have the ability to address to the individual word level using the
SA0 address, but the burst will continue in a linear sequence and wraps
around without incrementing the SA bits. Similarly when reading x18 and
x36 DDRll devices, the read burst will begin at the designated address,
but if the burst is started at any other position than the first word of the
burst, the burst will wrap back on itself and read the first locations before
completing. The x18 and x36 DDR II devices can also use the byte write
signals to prevent writing any individual bytes or word of the burst.
Output Enables
The DDRII SRAM automatically enables and disables the DQ[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the DQ outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and Vss to allow the SRAM to adjust its output drive
impedance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with V
DDQ
= 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to V
DDQ
.
6.42
2
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
Description
Data I/O signals. Data inputs are sampled on the rising edge of K and
K
during valid write operations. Data outputs are driven during a
valid read operation. The outputs are aligned with the rising edge of both C and
C
during normal operation. When operating in a single
clock mode (C and
C
tied high), the outputs are aligned with the rising edge of both K and
K.
When a Read operation is not initiated or
LD
is high (deselected) during the rising edge of K, DQ[X:O] are automatically driven to high impedance after any previous read
operation in progress completes.
1M x 18 -- DQ[17:0]
512K x 36 -- DQ[35:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of
K
clocks during
write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written
remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the
corresponding byte of data to be ignored and not written in to the device.
1M x 18 --
BW
0
controls DQ[8:0] and
BW
1
controls DQ[17:9]
512K x 36 --
BW
0
controls DQ[8:0],
BW
1
controls DQ[17:9],
BW
2
controls DQ[26:18] and
BW
3
controls DQ[35:27]
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
Burst count address bit on x18 and x36 DDRll devices. This bit allows changing the burst order in read or write operations, or
addressing to the individual word of a burst. See page 9 for all possible burst sequences.
Load Control Logic: Sampled on the rising edge of K. If
LD
is low, a two word burst read or write operation will initiate as designated by
the R/W input. If
LD
is high during the rising edge of K, operations in progress will complete, but new operations will not be initiated.
Read or Write Control Logic. If
LD
is low during the rising edge of K, the R/ indicates whether a new operation should be a read or
W
write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be initiated. If the
LD
input is high during the
rising edge of K, the R/W input will be ignored.
Positive Output Clock Input. C is used in conjunction with
C
to clock out the Read data from the device. C and
C
can be used together
to deskew the flight times of various devices on the board back to the controller. See application example for further details.
Negative Output Clock Input.
C
is used in conjunction with C to clock out the Read data from the device. C and
C
can be used together
to deskew the flight times of various devices on the board back to the controller. See application example for further details.
Positive Input Clock. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through DQ[X:0]
when in single clock mode. All accesses are initiated on the rising edge of K.
Negative Input Clock.
K
is used to capture synchronous inputs being presented to the device and to drive out data through DQ[X:0]
when in single clock mode.
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be
used as a data valid indication. These signals are free running and do not stop when the output data is three stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. DQ[X:0] output
impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly
to V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
6112 tbl 02a
DQ[X:0]
Input/Output
Synchronous
BW
0
,
BW
1,
BW
2
,
BW
3
Input
Synchronous
SA
SA
0
Input
Synchronous
Input
Synchronous
Input
Synchronous
LD
R/
W
Input
Synchronous
C
Input Clock
C
K
K
CQ,
CQ
Input Clock
Input Clock
Input Clock
Output Clock
Input
ZQ
6.42
3
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Definitions continued
Symbol
Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will
be different from those listed in this data sheet. There will be an increased propagation delay from the incidence of
C and
C
to DQ, or K and
K
to DQ as configured. The propagation delay is not a tested parameter, but will be
similar to the propagation delay of other SRAM devices in this speed grade.
TDO pin for JTAG
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to V
DD
when the pin is unconnected.
TMS pin for JTAG. An internal resistor will pull TMS to V
DD
when the pin is unconnected.
No connects inside the package. Can be tied to any voltage level.
Reference Voltage input. Static input used to set the reference level for HSTL inputs and outputs as well as AC
measurement points.
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Ground for the device. Should be connected to ground of the system.
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to
the desired output voltage.
6112 tbl 02b
Dof
f
Input
TDO
TCK
TDI
TMS
NC
V
REF
V
DD
V
SS
V
DDQ
Output
Input
Input
Input
No Connect
Input Reference
Power Supply
Ground
Power Supply
6.42
4
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Pin Configuration IDT71P71804 (1M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Dof
f
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/
SA
(2)
DQ
9
NC
NC
NC
DQ
12
NC
V
REF
NC
NC
DQ
15
NC
NC
NC
TCK
3
SA
NC
NC
DQ
10
DQ
11
NC
DQ
13
V
DDQ
NC
DQ
14
NC
NC
DQ
16
DQ
17
SA
4
R/
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/
SA
(1)
NC
DQ
7
NC
NC
NC
NC
V
REF
DQ
4
NC
NC
DQ
1
NC
NC
TMS
11
CQ
DQ
8
NC
NC
DQ
6
DQ
5
NC
ZQ
NC
DQ
3
DQ
2
NC
NC
DQ
0
TDI
6112 tbl 12b
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address. This must be tied or driven to Vss on the 1M x 18 DDRII Burst of 2 (71P71804) devices.
2. A2 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII Burst of 2 (71P71804) devices.
6.42
5
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