www.fairchildsemi.com
FAN4803
8-Pin PFC and PWM Controller Combo
Features
• Internally synchronized PFC and PWM in one 8-pin IC
• Patented one-pin voltage error amplifier with advanced
input current shaping technique
• Peak or average current, continuous boost, leading edge
PFC (Input Current Shaping Technology)
• High efficiency trailing-edge current mode PWM
• Low supply currents; start-up: 150µA typ., operating:
2mA typ.
• Synchronized leading and trailing edge modulation
• Reduces ripple current in the storage capacitor between
the PFC and PWM sections
• Overvoltage, UVLO, and brownout protection
• PFC V
CC
OVP with PFC Soft Start
General Description
The FAN4803 is a space-saving controller for power factor
corrected, switched mode power supplies that offers very
low start-up and operating currents.
Power Factor Correction (PFC) offers the use of smaller, lower
cost bulk capacitors, reduces power line loading and stress on
the switching FETs, and results in a power supply fully compli-
ant to IEC1000-3-2 specifications. The FAN4803 includes
circuits for the implementation of a leading edge, average
current “boost” type PFC and a trailing edge, PWM.
The FAN4803-1’s PFC and PWM operate at the same
frequency, 67kHz. The PFC frequency of the FAN4803-2 is
automatically set at half that of the 134kHz PWM. This
higher frequency allows the user to design with smaller
PWM components while maintaining the optimum operating
frequency for the PFC. An overvoltage comparator shuts
down the PFC section in the event of a sudden decrease in
load. The PFC section also includes peak current limiting for
enhanced system reliability.
Block Diagram
7
VEAO
4
35µA
–1
7V
+
–
PFC OFF
VCC
17.5V
16.2V
+
–
REF
VCC OVP
COMP
VREF
GND
2
COMP
M3
M4
PFC
CONTROL
LOGIC
PFC OUT
1
M1
M2
R1
M7
C1
30pF
LEADING
EDGE PFC
ONE PIN ERROR AMPLIFIER
3
ISENSE
–4
+
+
PFC ILIMIT
VCC
–
COMP
SOFT START
TRAILING
EDGE PWM
–1V
–
PFC/PWM UVLO
OSCILLATOR
PFC – 67kHz
PWM – 134kHz
–
VREF
VDC
26k
DUTY CYCLE
LIMIT
5
PWM COMPARATOR
PWM
CONTROL
LOGIC
40k
1.2V
6
ILIMIT
COMP
+
–
COMP
PWM OUT
8
+
M6
1.5V
–
+
DC ILIMIT
REV. 1.2.3 11/2/04
FAN4803
PRODUCT SPECIFICATION
Pin Configuration
FAN4803
8-Pin PDIP (P08)
8-Pin SOIC (S08)
PFC OUT
GND
ISENSE
VEAO
1
2
3
4
TOP VIEW
8
7
6
5
PWM OUT
VCC
ILIMIT
VDC
Pin Description
Pin
1
2
3
4
5
6
7
8
Name
PFC OUT
GND
I
SENSE
VEAO
V
DC
I
LIMIT
V
CC
PWM OUT
PFC driver output
Ground
Current sense input to the PFC current limit comparator
PFC one-pin error amplifier input
PWM voltage feedback input
PWM current limit comparator input
Positive supply (may require an external shunt regulator)
PWM driver output
Function
Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum
ratings are stress ratings only and functional device operation is not implied.
Parameter
I
CC
Current (average)
V
CC
MAX
I
SENSE
Voltage
Voltage on Any Other Pin
Peak PFC OUT Current, Source or Sink
Peak PWM OUT Current, Source or Sink
PFC OUT, PWM OUT Energy Per Cycle
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)
Thermal Resistance (
θ
JA
)
Plastic DIP
Plastic SOIC
Min
Max
40
18.3
1
V
CC
+ 0.3
1
1
1.5
150
150
260
110
160
Unit
mA
V
V
V
A
A
µJ
°C
°C
°C
°C/W
°C/W
-5
GND – 0.3
-65°
Operating Conditions
Temperature Range
FAN4803CS-X
FAN4803CP-X
0°C to 70°C
0°C to 70°C
2
REV. 1.2.3 11/2/04
PRODUCT SPECIFICATION
FAN4803
Electrical Characteristics
Unless otherwise specified, V
CC
= 15V, T
A
= Operating Temperature Range (Note 1)
Symbol
Parameter
One-pin Error Amplifier
V
EAO
Output Current
Line Regulation
V
CC
OVP Comparator
Threshold Voltage
PFC I
LIMIT
Comparator
Threshold Voltage
Delay to Output
DC I
LIMIT
Comparator
Threshold Voltage
Delay to Output
Oscillator
Initial Accuracy
Voltage Stability
Temperature Stability
Total Variation
Dead Time
PFC
Minimum Duty Cycle
Maximum Duty Cycle
Output Low Impedance
Output Low Voltage
Output High Impedance
Output High Voltage
Rise/Fall Time
PWM
Duty Cycle Range
Output Low Impedance
Output Low Voltage
Output High Impedance
Output High Voltage
Rise/Fall Time
Supply
V
CC
Clamp Voltage (V
CCZ
)
Start-up Current
I
CC
= 10mA
V
CC
= 11V, C
L
= 0
16.7
17.5
0.2
2.5
12
2.9
18.3
0.4
4
12.5
3.4
V
mA
mA
V
V
I
OUT
= 100mA, V
CC
= 15V
C
L
= 1000pF
13.5
I
OUT
= –100mA
I
OUT
= –10mA, V
CC
= 8V
FAN4803-2
FAN4803-1
0-41
0-49.5
0-47
8
0.8
0.7
8
14.2
50
0-50
0-50
15
1.5
1.5
15
%
%
Ω
V
V
Ω
V
ns
I
OUT
= 100mA, V
CC
= 15V
C
L
= 1000pF
13.5
V
EAO
> 7.0V,I
SENSE
= -0.2V
V
EAO
< 4.0V,I
SENSE
= 0V
I
OUT
= –100mA
I
OUT
= –10mA, V
CC
= 8V
90
95
8
0.8
0.7
8
14.2
50
0
15
1.5
1.5
15
%
%
Ω
V
V
Ω
V
ns
Conditions
T
A
= 25°C, V
EAO
= 6V
10V < V
CC
< 15V, V
EAO
= 6V
15.5
-0.9
Min
34.0
TYP
36.5
0.1
16.3
-1
150
1.5
150
67
1
2
67
0.45
MAX UNITS
39.0
0.3
16.8
-1.15
300
1.6
300
74
µA
µA
V
V
ns
V
ns
kHz
%
%
kHz
µs
1.4
T
A
= 25°C
10V < V
CC
< 15V
Over Line and Temp
PFC Only
60
60
0.3
74.5
0.65
Operating Current
V
CC
= 15V, C
L
= 0
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
11.5
2.4
Note:
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
REV. 1.2.3 11/2/04
3
FAN4803
PRODUCT SPECIFICATION
Functional Description
The FAN4803 consists of an average current mode boost
Power Factor Corrector (PFC) front end followed by a syn-
chronized Pulse Width Modulation (PWM) controller. It is
distinguished from earlier combo controllers by its low pin
count, innovative input current shaping technique, and very
low start-up and operating currents. The PWM section is
dedicated to peak current mode operation. It uses conven-
tional trailing-edge modulation, while the PFC uses leading-
edge modulation. This patented Leading Edge/Trailing Edge
(LETE) modulation technique helps to minimize ripple cur-
rent in the PFC DC buss capacitor.
The FAN4803 is offered in two versions. The FAN4803-1
operates both PFC and PWM sections at 67kHz, while the
FAN4803-2 operates the PWM section at twice the fre-
quency (134kHz) of the PFC. This allows the use of smaller
PWM magnetics and output filter components, while mini-
mizing switching losses in the PFC stage.
In addition to power factor correction, several protection fea-
tures have been built into the FAN4803. These include soft
start, redundant PFC over-voltage protection, peak current
limiting, duty cycle limit, and under voltage lockout
(UVLO). See Figure 12 for a typical application.
control of the PWM stage. The current ramp is offset inter-
nally by 1.2V and then compared against the opto feedback
voltage to set the PWM duty cycle.
PFC OUT and PWM OUT
PFC OUT and PWM OUT are the high-current power driv-
ers capable of directly driving the gate of a power MOSFET
with peak currents up to ±1A. Both outputs are actively held
low when V
CC
is below the UVLO threshold level.
V
CC
V
CC
is the power input connection to the IC. The V
CC
start-
up current is 150µA . The no-load I
CC
current is 2mA. V
CC
quiescent current will include both the IC biasing currents
and the PFC and PWM output currents. Given the operating
frequency and the MOSFET gate charge (Qg), average
PFC and PWM output currents can be calculated as I
OUT
=
Qg x F. The average magnetizing current required for any
gate drive transformers must also be included. The V
CC
pin
is also assumed to be proportional to the PFC output voltage.
Internally it is tied to the V
CC
OVP comparator (16.2V)
providing redundant high-speed over-voltage protection
(OVP) of the PFC stage. V
CC
also ties internally to the
UVLO circuitry, enabling the IC at 12V and disabling it at
9.1V. V
CC
must be bypassed with a high quality ceramic
bypass capacitor placed as close as possible to the IC.
Good bypassing is critical to the proper operation of the
FAN4803.
V
CC
is typically produced by an additional winding off the
boost inductor or PFC Choke, providing a voltage that is pro-
portional to the PFC output voltage. Since the V
CC
OVP max
voltage is 16.2V, an internal shunt limits V
CC
overvoltage to
an acceptable value. An external clamp, such as shown in
Figure 1, is desirable but not necessary.
VCC
Detailed Pin Descriptions
V
EAO
This pin provides the feedback path which forces the PFC
output to regulate at the programmed value. It connects to
programming resistors tied to the PFC output voltage and is
shunted by the feedback compensation network.
I
SENSE
This pin ties to a resistor or current sense transformer which
senses the PFC input current. This signal should be negative
with respect to the IC ground. It internally feeds the pulse-
by-pulse current limit comparator and the current sense feed-
back signal. The I
LIMIT
trip level is –1V. The I
SENSE
feed-
back is internally multiplied by a gain of four and compared
against the internal programmed ramp to set the PFC duty
cycle. The intersection of the boost inductor current
downslope with the internal programming ramp determines
the boost off-time.
1N4148
1N4148
1N5246B
V
DC
This pin is typically tied to the feedback opto-collector. It is
tied to the internal 5V reference through a 26k
Ω
resistor and
to GND through a 40k
Ω
resistor.
GND
Figure 1. Optional V
CC
Clamp
I
LIMIT
This pin is tied to the primary side PWM current sense resis-
tor or transformer. It provides the internal pulse-by-pulse
current limit for the PWM stage (which occurs at 1.5V) and
the peak current mode feedback path for the current mode
4
V
CC
is internally clamped to 16.7V minimum, 18.3V maxi-
mum. This limits the maximum V
CC
that can be applied to
the IC while allowing a V
CC
which is high enough to trip the
V
CC
OVP. The max current through this zener is 10mA.
External series resistance is required in order to limit the
current through this Zener in the case where the V
CC
voltage
exceeds the zener clamp level.
REV. 1.2.3 11/2/04
PRODUCT SPECIFICATION
FAN4803
GND
GND is the return point for all circuits associated with
this part. Note: a high-quality, low impedance ground is
critical to the proper operation of the IC. High frequency
grounding techniques should be used.
Power Factor Correction
Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current drawn
from the line is in phase with, and proportional to, the line
voltage. This is defined as a unity power factor is (one). A
common class of nonlinear load is the input of a most power
supplies, which use a bridge rectifier and capacitive input fil-
ter fed from the line. Peak-charging effect, which occurs on
the input filter capacitor in such a supply, causes brief high-
amplitude pulses of current to flow from the power line,
rather than a sinusoidal current in phase with the line volt-
age. Such a supply presents a power factor to the line of less
than one (another way to state this is that it causes significant
current harmonics to appear at its input). If the input current
drawn by such a supply (or any other nonlinear load) can be
made to follow the input voltage in instantaneous amplitude,
it will appear resistive to the AC line and a unity power factor
will be achieved.
To hold the input current draw of a device drawing power
from the AC line in phase with, and proportional to, the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous line
voltage. The PFC section of the FAN4803 uses a boost-
mode DC-DC converter to accomplish this. The input to the
converter is the full wave rectified AC line voltage. No filter-
ing is applied following the bridge rectifier, so the input
voltage to the boost converter ranges, at twice line frequency,
from zero volts to the peak value of the AC input and back to
zero. By forcing the boost converter to meet two simulta-
neous conditions, it is possible to ensure that the current that
the converter draws from the power line matches the instan-
taneous line voltage. One of these conditions is that the
output voltage of the boost converter must be set higher than
the peak value of the line voltage. A commonly used value is
385VDC, to allow for a high line of 270VAC
RMS
. The other
condition is that the current that the converter is allowed to
draw from the line at any given instant must be proportional
to the line voltage.
Since the boost converter topology in the FAN4803 PFC is
of the current-averaging type, no slope compensation is
required.
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn ON right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modu-
lation is determined during the ON time of the switch. Figure
2 shows a typical trailing edge control scheme.
L1
+
DC
I1
VIN
SW2
I2
I3
I4
SW1
C1
RL
RAMP
VEAO
REF
U3
+
EA
–
DFF
RAMP
OSC
U4
CLK
+
–
U1
R
Q
D U2
Q
CLK
VSW1
TIME
TIME
Figure 2. Typical Trailing Edge Control Scheme.
REV. 1.2.3 11/2/04
5
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