74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 03 — 12 June 2008
Product data sheet
1. General description
The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input
(CP) and an output enable input (OE) are common to all flip-flops.
The eight flip-flops will store the state of their individual D inputs that meet the set-up and
hold times requirements for the LOW-to-HIGH CP transition.
When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is
HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
2. Features
I
I
I
I
I
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Common 3-state output enable input
Input levels:
N
For 74AHC374: CMOS level
N
For 74AHCT374: TTL level
I
ESD protection:
N
HBM EIA/JESD22-A114E exceeds 2000 V
N
MM EIA/JESD22-A115-A exceeds 200 V
N
CDM EIA/JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
Nexperia
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AHC374
74AHC374D
74AHC374PW
74AHCT374
74AHCT374D
74AHCT374PW
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
TSSOP20
plastic small outline package; 20 leads; body
width 7.5 mm
SOT163-1
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
TSSOP20
plastic small outline package; 20 leads; body
width 7.5 mm
SOT163-1
Name
Description
Version
Type number
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
4. Functional diagram
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
FF1
to
FF8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
2
5
6
9
Q4 12
Q5 15
Q6 16
Q7 19
11 CP
1 OE
mna892
Fig 1.
Functional diagram
74AHC_AHCT374_3
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 03 — 12 June 2008
2 of 17
Nexperia
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
1
11
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
mna891
EN
C1
2
5
6
9
12
15
16
19
mna196
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
17
18
4
7
8
13
14
1D
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna893
Fig 4.
Logic diagram
74AHC_AHCT374_3
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 03 — 12 June 2008
3 of 17
Nexperia
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
001aad040
374
GND 10
Fig 5.
Pin configuration SO20 and TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
CP
Q4
D4
D5
Q5
Q6
D6
D7
Q7
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Description
3-state output enable input (active LOW)
3-state flip-flop output
data input
data input
3-state flip-flop output
3-state flip-flop output
data input
data input
3-state flip-flop output
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
3-state flip-flop output
data input
data input
3-state flip-flop output
3-state flip-flop output
data input
data input
3-state flip-flop output
supply voltage
74AHC_AHCT374_3
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 03 — 12 June 2008
4 of 17
Nexperia
74AHC374; 74AHCT374
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
Table 3.
Function table
[1]
Control
OE
Load and read register
Load register and disable outputs
L
L
H
H
[1]
Operating mode
Input
CP
↑
↑
↑
↑
Dn
l
h
l
h
Internal
flip-flop
L
H
L
H
Output
Q0 to Q7
L
H
Z
Z
H = HIGH voltage level;
h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition;
X = don’t care;
↑
= LOW-to-HIGH CP transition;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
−20
−20
−25
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO20 packages: above 70
°C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP20 packages: above 60
°C
the value of P
tot
derates linearly at 5.5 mW/K.
74AHC_AHCT374_3
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 03 — 12 June 2008
5 of 17
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