NLAS44599
Low Voltage Single Supply
Dual DPDT Analog Switch
The NLAS44599 is an advanced dual−independent CMOS double
pole−double throw (DPDT) analog switch fabricated with silicon
gate CMOS technology. It achieves high speed propagation delays
and low ON resistances while maintaining CMOS low power
dissipation. This DPDT controls analog and digital voltages that may
vary across the full power−supply range (from V
CC
to GND).
The device has been designed so the ON resistance (R
ON
) is much
lower and more linear over input voltage than R
ON
of typical CMOS
analog switches.
The channel select input is compatible with standard CMOS outputs.
The channel select input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused
by supply voltage
−
input/output voltage mismatch, battery backup,
hot insertion, etc.
The NLAS44599 can also be used as a quad 2−to−1 multiplexer−
demultiplexer analog switch with two Select pins that each controls
two multiplexer−demultiplexers.
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MARKING
DIAGRAMS
16
1
16
QFN−16
MN SUFFIX
CASE 485G
AS
4459
ALYW
Current
Part Marking
1
C
ALYW
Previous
Part Marking*
*Previous releases of this device may be marked as
shown in this diagram.
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
NLAS
4459
ALYW
1
•
•
•
•
•
•
•
•
Channel Select Input Over−Voltage Tolerant to 5.5 V
Fast Switching and Propagation Speeds
Break−Before−Make Circuitry
Low Power Dissipation: I
CC
= 2
mA
(Max) at T
A
= 25°C
Diode Protection Provided on Channel Select Input
Improved Linearity and Lower ON Resistance over Input Voltage
Latch−up Performance Exceeds 300 mA
ESD Performance: Human Body Model; > 2000 V,
Machine Model; > 200 V
•
Chip Complexity: 158 FETs
•
Pb−Free Packages are Available
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2008
July, 2008
−
Rev. 14
1
Publication Order Number:
NLAS44599/D
NLAS44599
QFN−16 PACKAGE
COM A
NO A
0
NC D
1
V
CC
FUNCTION TABLE
Select AB or CD
L
H
On Channel
NC to COM
NO to COM
16
15
14
13
12
NC A
1
SAB
COM D
1
See TSSOP−16
Switch Configuration
2
11
10
NO D
0
SCD
NO B
0
COM B
3
NC C
1
4
9
COM C
NC B1
GND
NO C
0
0
1
2
COM A
0/1
TSSOP−16 PACKAGE
COM B
NO A
0
1
16
V
CC
SELECT CD
COM C
COM A
2
15
NC D1
COM D
U
2/3
U
U
2/3
X1
3
0
1
2
3
0/1
NC A
1
3
14
COM D
SELECT AB
4
13
NO D0
Figure 2. IEC Logic Symbol
NO B
0
5
12
SELECT CD
COM B
6
11
NC C
1
NC B
1
7
10
COM C
GND
8
9
NO C
0
Figure 1. Logic Diagram
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2
U
U
U
U
U
U
U
U
U
8
SELECT AB
X1
NO A
0
NC A
1
NO B
0
NC B
1
NO C
0
NC C
1
NO D
0
NC D
1
7
6
5
NLAS44599
MAXIMUM RATINGS
Symbol
V
CC
V
IS
V
IN
I
IK
P
D
T
STG
T
L
T
J
MSL
F
R
V
ESD
Positive DC Supply Voltage
Analog Input Voltage (V
NO
or V
COM
)
Digital Select Input Voltage
DC Current, Into or Out of Any Pin
Power Dissipation in Still Air
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30%
−
35%
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
Above V
CC
and Below GND at 125°C (Note 4)
QFN−16
TSSOP−16
QFN−16
TSSOP−16
Parameter
Value
*0.5
to
)7.0
*0.5 v
V
IS
v
V
CC
)0.5
*0.5 v
V
I
v)7.0
$50
800
450
*65
to
)150
260
+150
Level 1
UL 94−V0 (0.125 in)
2000
200
1000
$300
80
164
V
V
mA
mW
°C
°C
°C
Unit
V
I
Latch−Up
q
JA
Latch−Up Performance
Thermal Resistance
mA
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
IS
T
A
t
r
, t
f
DC Supply Voltage
Digital Select Input Voltage
Analog Input Voltage (NC, NO, COM)
Operating Temperature Range
Input Rise or Fall Time, SELECT
V
CC
= 3.3 V
$
0.3 V
V
CC
= 5.0 V
$
0.5 V
Parameter
Min
2.0
GND
GND
*55
0
0
Max
5.5
5.5
V
CC
)125
100
20
Unit
V
V
V
°C
ns/V
NORMALIZED FAILURE RATE
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature
5C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
T
J
= 130°C
T
J
= 120°C
T
J
= 100°C
T
J
= 110°C
T
J
= 90°C
T
J
= 80°C
100
TIME, YEARS
1
1
10
1000
Figure 3. Failure Rate vs. Time Junction Temperature
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3
NLAS44599
DC CHARACTERISTICS
−
Digital Section
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage, Select Inputs
Condition
V
CC
2.0
2.5
3.0
4.5
5.5
2.0
2.5
3.0
4.5
5.5
V
IN
= 5.5 V or GND
V
IN
= 5.5 V or GND
Select and V
IS
= V
CC
or GND
5.5
0
5.5
*555C
to 255C
1.5
1.9
2.1
3.15
3.85
0.5
0.6
0.9
1.35
1.65
$0.2
$10
4.0
t855C
1.5
1.9
2.1
3.15
3.85
0.5
0.6
0.9
1.35
1.65
$2.0
$10
4.0
t1255C
1.5
1.9
2.1
3.15
3.85
0.5
0.6
0.9
1.35
1.65
$2.0
$10
8.0
Unit
V
V
IL
Maximum Low−Level Input
Voltage, Select Inputs
V
I
IN
I
OFF
I
CC
Maximum Input Leakage
Current
Power Off Leakage Current,
Select Inputs
Maximum Quiescent Supply
Current
mA
mA
mA
DC ELECTRICAL CHARACTERISTICS
−
Analog Section
Guaranteed Limit
Symbol
R
ON
Parameter
Maximum “ON” Resistance
(Figures 17
−
23)
Condition
V
IN
= V
IL
or V
IH
V
IS
= GND to V
CC
I
IN
I
v
10.0 mA
V
IN
= V
IL
or V
IH
I
IN
I
v
10.0 mA
V
IS
= 1 V, 2 V, 3.5 V
V
IN
= V
IL
or V
IH
V
NO
or V
NC
= 1.0 V
COM
4.5 V
V
IN
= V
IL
or V
IH
V
NO
1.0 V or 4.5 V with V
NC
floating or
V
NO
1.0 V or 4.5 V with V
NO
floating
V
COM
= 1.0 V or 4.5 V
V
CC
2.5
3.0
4.5
5.5
4.5
*555C
to 255C
85
45
30
25
4
t855C
95
50
35
30
4
t1255C
105
55
40
35
5
Unit
W
R
FLAT (ON)
ON Resistance Flatness
(Figures 17
−
23)
NO or NC Off Leakage
Current (Figure 9)
COM ON Leakage Current
(Figure 9)
W
I
NC(OFF)
I
NO(OFF)
I
COM(ON)
5.5
5.5
1
1
10
10
100
100
nA
nA
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4
NLAS44599
AC ELECTRICAL CHARACTERISTICS
(Input t
r
= t
f
= 3.0 ns)
Guaranteed Maximum Limit
Symbol
t
ON
Parameter
Turn−On Time
(Figures 12 and 13)
Test Conditions
R
L
= 300
W,
C
L
= 35 pF
(Figures 5 and 6)
V
CC
(V)
2.5
3.0
4.5
5.5
2.5
3.0
4.5
5.5
2.5
3.0
4.5
5.5
V
IS
(V)
2.0
2.0
3.0
3.0
2.0
2.0
3.0
3.0
2.0
2.0
3.0
3.0
*555C
to 255C
Min
5
5
2
2
1
1
1
1
1
1
1
1
Typ*
23
16
11
9
7
5
4
3
12
11
6
5
Max
35
24
16
14
12
10
6
5
t855C
Min
5
5
2
2
1
1
1
1
1
1
1
1
Max
38
27
19
17
15
13
9
8
t1255C
Min
5
5
2
2
1
1
1
1
1
1
1
1
Max
41
30
22
20
18
16
12
11
Unit
ns
t
OFF
Turn−Off Time
(Figures 12 and 13)
R
L
= 300
W,
C
L
= 35 pF
(Figures 5 and 6)
ns
t
BBM
Minimum Break−Before−Make
Time
V
IS
= 3.0 V (Figure 4)
R
L
= 300
W,
C
L
= 35 pF
ns
Typical @ 25, V
CC
= 5.0 V
C
IN
C
NO
or C
NC
C
COM
C
(ON)
Maximum Input Capacitance, Select Input
Analog I/O (switch off)
Common I/O (switch off)
Feedthrough (switch on)
8
10
10
20
pF
*Typical Characteristics are at 25°C.
ADDITIONAL APPLICATION CHARACTERISTICS
(Voltages Referenced to GND Unless Noted)
Symbol
BW
Parameter
Maximum On−Channel
−3dB
Bandwidth or Minimum Frequency
Response (Figure 11)
Maximum Feedthrough On Loss
Condition
V
IN
=
0 dBm
V
IN
centered between V
CC
and GND
(Figure 7)
V
IN
=
0 dBm @ 100 kHz to 50 MHz
V
IN
centered between V
CC
and GND
(Figure 7)
f = 100 kHz; V
IS
=
1 V RMS
V
IN
centered between V
CC
and GND
(Figure 7)
V
IN =
V
CC to
GND, F
IS
= 20 kHz
t
r
= t
f
= 3 ns
R
IS
= 0
W,
C
L
= 1000 pF
Q = C
L
*
DV
OUT
(Figure 8)
F
IS
= 20 Hz to 100 kHz, R
L
= Rgen = 600
W,
C
L
= 50 pF
V
IS
= 5.0 V
PP
sine wave
f = 100 kHz; V
IS
=
1 V RMS
V
IN
centered between V
CC
and GND
(Figure 7)
V
CC
V
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
5.5
Typical
255C
145
170
175
−3
−3
−3
−93
−93
−93
1.5
3.0
Unit
MHz
V
ONL
dB
V
ISO
Off−Channel Isolation (Figure 10)
dB
Q
Charge Injection Select Input to
Common I/O (Figure 15)
pC
THD
VCT
Total Harmonic Distortion THD +
Noise (Figure 14)
Channel−to−Channel Crosstalk
%
5.5
5.5
3.0
0.1
dB
−90
−90
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