FemtoClock™ Dual VCXO Video PLL
810001-21
Data Sheet
General Description
The 810001-21 is a PLL based synchronous clock generator that is
optimized for digital video clock jitter attenuation and frequency
translation. The device contains two internal frequency multiplication
stages that are cascaded in series. The first stage is a VCXO PLL
that is optimized to provide reference clock jitter attenuation, and to
support the complex PLL multiplication ratios needed for video rate
conversion. The second stage is a FemtoClock™ frequency
multiplier that provides the low jitter, high frequency video output
clock.
Preset multiplication ratios are selected from internal lookup tables
using device input selection pins. The multiplication ratios are
optimized to support most common video rates used in professional
video system applications. The VCXO requires the use of an
external, inexpensive pullable crystal. Two crystal connections are
provided (pin selectable) so that both 60 and 59.94 base frame rates
can be supported. The VCXO requires external passive loop filter
components which are used to set the PLL loop bandwidth and
damping characteristics.
Features
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Jitter attenuation and frequency translation of video clock signals
Supports SMPTE 292M, ITU-R Rec. 601/656 and
MPEG-transport clocks
Support of High-Definition (HD) and Standard-Definition (SD)
pixel rates
Dual VCXO-PLL supports both 60 and 59.94Hz base frame rates
in one device
Supports both 1000/1001 and 1001/1000 rate conversions
Dual PLL mode for high-frequency clock generation (36MHz to
148.5MHz)
VCXO-PLL mode for low-frequency clock generation (27MHz and
26.973MHz)
One LVCMOS/LVTTL clock output
Two selectable LVCMOS/LVTTL clock inputs
LVCMOS/LVTTL compatible control signals
RMS phase jitter @148.3516MHz, (12kHz - 20MHz):
1.089ps (typical)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) packages
Supported Input Frequencies
f
VCXO
= 27MHz
27.0000MHz
27.0270MHz
74.1758MHz
74.3243MHz
74.2500MHz
27.0270MHz
26.9730MHz
74.1758MHz
45.0000kHz
33.7500kHz
15.6250kHz
15.7343kHz
28.1250kHz
f
VCXO
= 26.973MHz
26.9730MHz
27.0000MHz
74.1016MHz
74.2499MHz
74.1758MHz
27.0000MHz
26.9461MHz
74.1016kHz
44.9550kHz
33.7163kHz
15.6094kHz
15.7185kHz
28.0969kHz
Supported Output Frequencies
f
VCXO
= 27MHz
148.5000MHz
74.2500MHz
49.5000MHz
33.0000MHz
162.0000MHz
81.0000MHz
54.0000MHz
36.0000MHz
27.0000MHz
f
VCXO
= 26.973MHz
148.3515MHz
74.1758MHz
49.4505MHz
32.9670MHz
161.8380MHz
80.9190MHz
53.9460MHz
35.9640MHz
26.9730MHz
©2016 Integrated Device Technology, Inc
1
Revision B March 3, 2016
810001-21 Data Sheet
Block Diagram
XTAL_OUT0
XTAL_IN0
XTAL_IN1
XTAL_OUT1
Loop
Filter
0
CLK0
Pulldown
CLK1
Pulldown
CLK_SEL
Pulldown
V3:V0
Pulldown
4
VCXO
Divider
Table
VCXO Input
Pre-Divider
(P Value
from Table)
Phase
Detector
1
0
1
VCXO
Charge
Pump
VCXO Feedback Divider
(M Value from Table)
VCXO Jitter Attenuation PLL
Pulldown
XTAL_SEL
ISET
LF0
LF1
10
11
FemtoClock
Frequency Multiplier
0= x22 (default)
1= x24
01
10
11
Output
Divider
00 = 4
(default)
01 = 8
10 = 12
11 = 18
00
01
10
11
Q
Pullup
OE
MR
Pulldown
MF
Pulldown
N1:N0
Pulldown
nBP1:nBP0
Pullup
2
2
Master Reset
Pin Assignment
XTAL_OUT0
XTAL_OUT1
XTAL_IN0
XTAL_IN1
GND
XTAL_SEL
V
DDX
32 31 30 29 28 27 26 25
LF1
LF0
ISET
V
DD
nBP0
GND
CLK_SEL
CLK1
1
2
3
4
5
6
7
8
9
CLK0
V
DD
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
V1
V0
V
DD
MR
MF
V2
V3
N0
N1
nBP1
OE
GND
Q
V
DDO
V
DDA
810001-21
32 Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
©2016 Integrated Device Technology, Inc
2
Revision B March 3, 2016
810001-21 Data Sheet
Table 1. Pin Descriptions
Number
1, 2
3
4, 11, 25
5, 22
6, 20, 29
7
8, 9
10, 14,
15, 16
12
13
17
18
19
21
23, 24
26
27,
28
30,
31
32
Name
LF1, LF0
ISET
V
DD
nBP0,
nBP1
GND
CLK_SEL
CLK1, CLK0
V0, V1,
V2, V3
MR
MF
V
DDA
V
DDO
Q
OE
N1, N0
XTAL_SEL
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
V
DDX
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Power
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Description
Loop filter connection node pins.
Charge pump current setting pin.
Core supply pins.
PLL Bypass control pins. See block diagram.
Power supply ground.
Input clock select. When HIGH selects CLK1. When LOW, selects CLK0.
LVCMOS / LVTTL interface levels.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
VCXO PLL divider selection pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the output to go low. When logic LOW, the internal dividers and the
output is enabled. LVCMOS/LVTTL interface levels.
FemtoClock multiplication factor select pin. LVCMOS/LVTTL interface levels.
Analog supply pin.
Output supply pin.
Single-ended VCXO PLL clock output. LVCMOS/LVTTL interface levels.
Pullup
Pulldown
Pulldown
Output enable. When logic LOW, the clock output is in high-impedance. When
logic HIGH, the output is enabled. LVCMOS/LVTTL interface levels.
FemtoClock output divide select pins. LVCMOS/LVTTL interface levels.
Crystal select. When HIGH, selects XTAL1. When LOW, selects XTAL0.
LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output.
Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output.
Power supply pin for VCXO charge pump.
Input
Input
Power
Power
Output
Input
Input
Input
Input
Input
Power
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
V
DD
= V
DDO
= 3.465V
Test Conditions
Minimum
Typical
4
8.5
51
51
22.5
Maximum
Units
pF
pF
k
k
R
PULLDOWN
Input Pulldown Resistor
Output Impedance
©2016 Integrated Device Technology, Inc
3
Revision B March 3, 2016
810001-21 Data Sheet
Function Tables
Table 3A. VCXO PLL Pre- and Feedback Divider Function Table
Input
V3
0 (default)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
V2
0 (default)
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
V1
0 (default)
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
V0
0 (default)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VCXO PLL Configuration
Pre-Divider P
1000
1001
11000
11011
11000
4004
4004
1000
250
253
92
1
1
1
1
1
Feedback- Divider M
1000
1000
4004
4000
4000
4004
4000
1001
91
92
92
600
800
1728
1716
960
©2016 Integrated Device Technology, Inc
4
Revision B March 3, 2016
810001-21 Data Sheet
Table 3B. Input Frequency Table
Input
V3
0 (default)
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
V2
0 (default)
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
V1
0 (default)
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
V0
0 (default)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Crystal Frequency (f
VCXO
)
27MHz
27.0000MHz
27.0270MHz
74.1758MHz
74.3243MHz
74.2500MHz
27.0000MHz
27.0270MHz
26.9730MHz
74.1758MHz
74.2500MHz
27.0000MHz
45.0000kHz
33.7500kHz
15.6250kHz
15.7343kHz
28.1250kHz
26.973MHz
26.9730MHz
27.0000MHz
74.1016MHz
74.2499MHz
74.1758MHz
26.9730MHz
27.0000MHz
26.9461MHz
74.1016MHz
74.1758MHz
26.9730MHz
44.9550kHz
33.7163kHz
15.6094kHz
15.7185kHz
28.0969kHz
Table 3C. Output Frequency Table (dual PLL Mode)
FemtoClock Look-up Table
f
VCXO
MF
0
0
0
0
27MHz
1
1
1
1
0
0
0
0
26.973MHz
1
1
1
1
0
0
1
1
0
1
0
1
161.8380
80.9190
53.9460
35.9640
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
162.0000
81.0000
54.0000
36.0000
148.3515
74.1758
49.4505
32.9670
N1
0
0
1
1
N0
0
1
0
1
Output Frequency f
Q
(MHz)
148.5000
74.2500
49.5000
33.0000
NOTE: Use the VCXO-PLL mode to achieve output Frequencies of 27MHz or 26.973MHz. See Table 3H.
©2016 Integrated Device Technology, Inc
5
Revision B March 3, 2016
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