1:10 LVPECL Output Fanout Buffer
IDT8T53S111I
DATA SHEET
General Description
The IDT8T53S111I is a high-performance differential LVPECL fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The IDT8T53S111I
is characterized to operate from a 3.3V and 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the IDT8T53S111I ideal for those clock distribution
applications demanding well-defined performance and repeatability.
Two selectable differential inputs and ten low skew outputs are
available. The integrated V
REF
voltage generator enables easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Ten low skew, low additive jitter LVPECL outputs
Two selectable, differential LVPECL clock inputs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL and CML
Maximum input clock frequency: 2.5GHz
LVCMOS interface levels for the control input (input select)
Output skew: 15ps (typical)
Propagation delay: 250ps (typical)
Additive phase jitter, RMS; f
REF
= 156.25MHz (12kHz - 20MHz):
30fs (typical)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (I
EE
): 126mA
Lead-free (RoHS 6) 32-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Block Diagram
Q0
nQ0
Pin Assignment
24 23 22 21 20 19 18 17
16
15
14
13
12
11
10
9
1
V
CC
2
SEL
3
P C LK 0
4
nP C LK 0
5
VR E F
6
P C LK 1
7
nP C LK 1
8
V
EE
nQ6
V
CCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
V
CCO
nQ3
nQ4
nQ5
V
CCO
25
26
27
28
29
30
31
32
Q1
nQ1
Q2
nQ2
PCLK0
nPCLK0
Pulldown
PU / PD
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CCO
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
VOLTAGE
REFERENCE
Q8
nQ8
Q9
nQ9
0
1
PCLK1
nPCLK1
Pulldown
PU / PD
IDT8T53S111I
32-lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm E-Pad
NL Package, Top View
SEL
V
REF
Pulldown
IDT8T53S111NLGI
REVISION A JULY 12, 2012
1
©2012 Integrated Device Technology, Inc.
Q6
Q3
Q4
Q5
IDT8T53S111I Data Sheet
1:10 LVPECL OUTPUT FANOUTBUFFER
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 16,
25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
V
CC
SEL
PCLK0
nPCLK0
V
REF
PCLK1
nPCLK1
V
EE
V
CCO
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Output
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown
Pulldown/
Pullup
Pulldown
Pulldown
Pulldown/
Pullup
Type
Description
Power supply pin.
Reference select control. See Table 3 for function. LVCMOS/LVTTL interface
levels.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock input.
Bias voltage generator for the nPCLK[0:1] inputs in single-ended input signal
applications.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock input.
Negative power supply pin.
Output power supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Function Table
Table 3A. SEL Input Selection Function Table
Input
SEL
0 (default)
1
Operation
PCLK0, nPCLK0 is the selected differential clock input.
PCLK1, nPCLK1 is the selected differential clock input.
NOTE: SEL is an asynchronous control.
IDT8T53S111NLGI
REVISION A JULY 12, 2012
2
©2012 Integrated Device Technology, Inc.
IDT8T53S111I Data Sheet
1:10 LVPECL OUTPUT FANOUTBUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
I
REF
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
±2mA
48.9C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
95
Maximum
3.465
126
Units
V
mA
Table 4B. Power Supply DC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
90
Maximum
2.625
119
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
Input Low Voltage
Input High Current
Input Low Current
SEL
SEL
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
IDT8T53S111NLGI
REVISION A JULY 12, 2012
3
©2012 Integrated Device Technology, Inc.
IDT8T53S111I Data Sheet
1:10 LVPECL OUTPUT FANOUTBUFFER
Table 4D. LVPECL DC Characteristics,
V
CC
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High Current
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, PCLK1
Input Low Current
nPCLK0, nPCLK1
Reference Voltage for Input Bias
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
I
REF
= 2mA
-10
-150
V
CC
– 1.6
V
CCO
– 1.6
V
CCO
– 2.0
V
CC
– 1.1
V
CCO
– 0.6
V
CCO
– 1.3
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
NOTE: Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
to V
CCO
– 2V.
Table 4E. LVPECL DC Characteristics,
V
CC
= V
CCO
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High Current
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, PCLK1
Input Low Current
nPCLK0, nPCLK1
Reference Voltage for Input Bias
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
I
REF
= 2mA
-10
-150
V
CC
– 1.6
V
CCO
– 1.4
V
CCO
– 2.0
V
CC
– 1.1
V
CCO
– 0.8
V
CCO
– 1.4
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
NOTE: Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
to V
CCO
– 2V.
IDT8T53S111NLGI
REVISION A JULY 12, 2012
4
©2012 Integrated Device Technology, Inc.
IDT8T53S111I Data Sheet
1:10 LVPECL OUTPUT FANOUTBUFFER
AC Electrical Characteristics
Table 5. AC Electrical Characteristics,
V
CC
= V
CCO
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
REF
t
PD
tsk(o)
tsk(i)
tsk(p)
tsk(pp)
Parameter
Input
Frequency
PCLK[0:1],
nPCLK[0:1]
PCLK[0:1], nPCLK[0:1]
to any Q[0:9], nQ[0:9]
for V
PP
= 0.1V or 0.3V
196
250
15
5
f
REF
= 50MHz
14
17
Test Conditions
Minimum
Typical
Maximum
2.5
Units
GHz
Propagation Delay;
NOTE 1
Output Skew; NOTE 2, 3
Input Skew; NOTE 3
Pulse Skew
Part-to-Part Skew;
NOTE 3, 4
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
Output Rise/ Fall Time
MUX Isolation; NOTE 5
Input Peak-to-Peak
Voltage; NOTE 5
Common Mode Input
Voltage; NOTE 6, 7
Output Voltage Swing,
Peak-to-Peak
Differential Output Voltage
Swing, Peak-to-Peak
300
50
25
38
115
ps
ps
ps
ps
ps
t
JIT
t
R
/ t
F
MUX
ISOLATION
V
PP
V
CMR
V
O(PP)
V
DIFF_OUT
f
REF
= 156.52MHz
Integration Range: 12kHz – 20MHz
20% to 80%
f
REF
= 100MHz
f
1.5GHz
f > 1.5GHz
0.1
0.2
1.0
f
REF
2GHz
f
REF
2GHz
0.5
1.0
50
30
120
fs
90
-75
160
1.5
1.5
V
CCO
– 0.3
ps
dB
V
V
V
V
V
0.65
1.3
0.8
1.6
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential
crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, temperature, frequency and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 5: Qx, nQx outputs measured differentially. See
MUX Isolation diagram
in the
Parameter Measurement Information section.
NOTE 6: V
IL
should not be less than -0.3V.
NOTE 7: Common mode input voltage is defined as the crosspoint.
IDT8T53S111NLGI
REVISION A JULY 12, 2012
5
©2012 Integrated Device Technology, Inc.
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