IRS2011(S)PBF
High and Low Side Driver
Features
Floating channel designed for bootstrap operation
Fully operational to 200V
Tolerant to negative transient voltage, dV/dt immune
Gate drive supply range from 10 to 20V
Independent low and high side channels
Input logic HIN/LIN active high
Undervoltage lockout for both channels
3.3V and 5V logic compatible
CMOS Schmitt-triggered inputs with pull-down
Matched propagation delay for both channels
Product Summary
V
OFFSET
(max)
I
O+/-
(typ)
V
OUT
t
on/off
(typ)
Delay Matching (max)
200V
1.0A / 1.0A
10 – 20V
60ns
20ns
Description
The IRS2011 is a high power, high speed power MOSFET
driver with independent high and low side referenced output
channels. Logic inputs are compatible with standard CMOS
or LSTTL output, down to 3.3V logic. The output drivers
feature a high pulse current buffer stage designed for
minimum driver cross-conduction. Propagation delays are
matched to simplify use in high frequency applications. The
floating channel can be used to drive an N-channel power
MOSFET in the high side configuration which operates up to
200 volts. Proprietary HVIC and latch immune CMOS
technologies enable ruggedized monolithic construction.
Package Options
8-Lead PDIP
8-Lead SOIC
Applications
Converters
DC motor drive
Ordering Information
Base Part Number
IRS2011PBF
IRS2011SPBF
IRS2011SPBF
Standard Pack
Package Type
PDIP8
SO8N
SO8N
Form
Tube
Tube
Tape and Reel
Quantity
50
95
2500
Orderable Part Number
IRS2011PBF
IRS2011SPBF
IRS2011STRPBF
1
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Typical Connection Diagram
(Refer to Lead Assignments for correct configuration.) This diagram shows electrical connections only. Please refer to our Application Notes
and Design Tips for proper circuit board layout.
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
dV
s
/dt
P
D
Rth
JA
T
J
T
S
T
L
†
Definition
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
Logic input voltage (HIN, LIN)
Allowable offset supply voltage transient
8-Lead PDIP
Package power dissipation
@ T
A
≤ +25°C
8-Lead SOIC
8-Lead PDIP
Thermal resistance, junction to
ambient
8-Lead SOIC
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
Min.
-0.3
V
B
- 20
V
S
- 0.3
-0.3
-0.3
-0.3
—
—
—
—
—
—
-55
—
Max.
†
220
V
B
+ 0.3
V
B
+ 0.3
†
20
V
CC
+ 0.3
V
CC
+ 0.3
50
1.0
0.625
125
200
150
150
300
Units
V
V/ns
W
°C/W
°C
All supplies are fully tested at 25V and an internal 20V clamp exists for each supply
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. The V
S
and COM offset
ratings are tested with all supplies biased at 15V differential.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
IN
T
A
††
Definition
High side floating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side fixed supply voltage
Low side output voltage
Logic input voltage (HIN, LIN)
Ambient temperature
Min.
V
S
+ 10
††
Max.
V
S
+ 20
200
V
B
20
V
CC
V
CC
125
Units
V
S
10
0
COM
-40
V
°C
Logic operational for V
S
of -5 to +200V. Logic state held for V
S
of -5V to -V
BS
.
3
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, C
L
= 1000pF and T
A
= 25°C unless otherwise specified. Figure 1 shows the timing
definitions.
Symbol
t
on
t
off
t
r
t
f
DM1
DM2
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
Turn-on delay matching
| t
on
(H) - t
on
(L) |
Turn-off delay matching
| t
off
(H) - t
off
(L) |
Min.
—
—
—
—
—
—
Typ.
60
60
25
15
—
—
Max.
80
80
40
35
20
20
Units
Test Conditions
V
S
= 0V
V
S
= 200V
ns
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V and T
A
= 25°C unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters are referenced to
COM and are applicable to all logic input leads: HIN and LIN. The V
O
and I
O
parameters are referenced to COM
and are applicable to the respective output leads: HO or LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
BSUV+
V
BSUV-
V
CCUV+
V
CCUV-
I
O+
I
O-
Definition
Logic “1” input voltage
Logic “0” input voltage
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input bias current
Logic “0” input bias current
V
BS
supply undervoltage positive
going threshold
V
BS
supply undervoltage negative
going threshold
V
CC
supply undervoltage positive
going threshold
V
CC
supply undervoltage negative
going threshold
Output high short circuit pulsed
current
Output low short circuit pulsed
current
Min.
2.5
—
—
—
—
—
—
—
—
8.3
7.5
8.3
7.5
—
—
Typ.
—
—
—
—
—
120
200
3
—
9.0
8.2
9.0
8.2
1.0
1.0
Max.
—
0.7
1.4
0.1
50
210
300
10
5
9.7
8.9
V
9.7
8.9
—
A
—
V
O
= 0V,
PW ≤ 10 μs
V
O
= 15V
PW ≤ 10 μs
Units
Test Conditions
V
CC
= 10V – 20V
V
I
O
= 0A
I
O
= 20mA
V
B
= V
S
= 200V
V
IN
= 0V or 3.3V
V
IN
= 3.3V
V
IN
= 0V
μA
4
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© 2015 International Rectifier
October 28, 2015
IRS2011(S)PBF
Functional Block Diagram
5
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© 2015 International Rectifier
October 28, 2015
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