TB62777FNG/FG
TOSHIBA Bi-CMOS Integrated Circuit
Silicon Monolithic
TB62777FNG, TB62777FG
8-Channel Constant-Current LED Driver of the 3.3-V and 5-V Power Supply Voltage
Operation
The TB62777FNG/FG is comprised of constant-current drivers
designed for LEDs and LED panel displays.
The regulated current sources are designed to provide a
constant current, which is adjustable through one external
resistor.
The TB62777FNG/FG incorporates eight channels of shift
registers, latches, AND gates and constant-current outputs.
Fabricated using the Bi-CMOS process, the TB62777FNG/FG is
capable of high-speed data transfers.
The TB62777FNG/FG is RoHS.
TB62777FNG
TB62777FG
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Power supply voltages: V
DD
=
3.3 V/5 V
Output drive capability and output count: 50 mA
×
8 channels
Constant-current output range: 5 to 40 mA
Voltage applied to constant-current output terminals: 0.4 V
(min, I
OUT
=
5 to 40 mA)
Designed for common-anode LEDs
Thermal shutdown (TSD)（min: 150℃）
Power on reset (POR)
Logical input signal voltage level: 3.3-V and 5-V CMOS
interfaces (Schmitt trigger input)
Maximum output voltage: 25V
Serial data transfer rate: 25 MHz (max) @cascade connection
Operating temperature range: T
opr
= −40
to 85°C
Package: SSOP16-P-225-0.65B/ SSOP16-P-225-1.00A
Constant-current accuracy
Output Voltage
0.4 V to 4 V
Current accuracy
Between Channels
±3%
Current Accuracy
Between ICs
±6%
Output Current
15 mA
Weight: SSOP16-P-225-0.65B 0.07 g (typ.)
SSOP16-P-225-1.00A 0.14 g
(typ.)
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2010-03-08
TB62777FNG/FG
Pin Assignment
(top view)
GND
SERIAL-IN
CLOCK
LATCH
OUT0
OUT1
OUT2
OUT3
VDD
R-EXT
SERIAL-OUT
ENABLE
OUT7
OUT6
OUT5
OUT4
Block Diagram
OUT0
OUT1
OUT7
R-EXT
I-REG
TSD
VDD
POR
ENABLE
Q
ST R D
LATCH
Q
ST R D
Q
ST R D
GND
SERIAL-IN
D0
Q0
Q1
Q7
8-bit shift register
D0 to D7
R
CLOCK
SERIAL-OUT
D
Q
CK R
Truth Table
CLOCK
LATCH
ENABLE
SERIAL-IN
OUT0
…
OUT5
…
OUT7
Dn
…
Dn
−
5
…
Dn
−
7
No Change
Dn
+
2
…
Dn
−
3
…
Dn
−
5
OFF
OFF
SERIAL-OUT
No change
No change
No change
No change
Dn
－
4
H
L
H
X
X
L
L
L
H
H
Dn
Dn
+
1
Dn
+
2
Dn
+
3
Dn
+
3
Note 1:
OUT0
to
OUT7
=
On when Dn
=
H;
OUT0
to
OUT7
=
Off when Dn
=
L.
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2010-03-08
TB62777FNG/FG
Timing Diagram
n
=
0
CLOCK
L
H
1
2
3
4
5
6
7
H
SERIAL-IN
L
H
LATCH
L
H
ENABLE
L
ON
OUT0
OFF
ON
OUT1
OFF
ON
OUT 2
OFF
ON
OUT7
OFF
H
SERIAL-OUT
Data applied when n
=
0
L
Note 1: Latches are level-sensitive, not edge-triggered.
Note 2: The TB62777FNG can be used at 3.3 V or 5.0 V. However, the V
DD
supply voltage must be equal to the input
voltage.
Note 3: Serial data is shifted out of SERIAL-OUT on the falling edge of CLOCK.
Marks:
The latches hold data while the LATCH terminal is held Low. When the LATCH terminal is High, the
latches do not hold data and pass it transparently. When the
ENABLE terminal is Low,
OUT0
to
OUT7
toggle between ON and OFF according to the data. When the ENABLE terminal is High,
OUT0
to
OUT7
are forced OFF.
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2010-03-08
TB62777FNG/FG
Terminal Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
GND
SERIAL-IN
CLOCK
LATCH
Function
GND terminal
Serial data input terminal
Serial clock input terminal
Latch input terminal
Constant-current output terminal (Open collector)
Constant-current output terminal (Open collector)
Constant-current output terminal (Open collector)
Constant-current output terminal (Open collector)
Constant-current output terminal (Open collector)
Constant-current output terminal (Open collector)
Constant-current output terminal (Open collector)
Constant-current output terminal (Open collector)
Output enable input terminal
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
ENABLE
SERIAL-OUT
R-EXT
V
DD
All outputs (
OUT0
to
OUT7
) are disabled when the ENABLE terminal is driven High, and
enabled when it is driven Low.
Serial data output terminal. Serial data is clocked out on the falling edge of CLOCK.
An external resistor is connected between this terminal and ground.
OUT0
to
OUT7
are adjusted
to the same current value.
Power supply terminal
Equivalent Circuits for Inputs and Outputs
CLOCK, SERIAL-IN
，
ENABLE
，
LATCH
Terminals
V
DD
CLOCK
SERIAL-IN
ENABLE
LATCH
GND
GND
V
DD
SERIAL-OUT Terminal
SERIAL-OUT
OUT0 to OUT7 Constant-current
Output Terminals
OUT0
~ OUT7
GND
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2010-03-08
TB62777FNG/FG
Absolute Maximum Ratings
(Ta
=
25°C)
Characteristics
Supply voltage
Input voltage
Output current
Output voltage
Power dissipation
Thermal resistance
Operating temperature range
Storage temperature range
Maximum junction temperature
Symbol
V
DD
V
IN
I
OUT
V
OUT
P
d
R
th (j-a)
T
opr
T
stg
T
j
Rating
6.0
−
0.3 to V
DD
+
0.3 (Note 1)
Unit
V
V
mA/ch
V
(Notes 2 and 3)
(Note 2)
W
°C/W
°C
°C
°C
55
−
0.3 to 25
1.19(FG TYPE) / 1.02(FNG TYPE)
105(FG TYPE) / 122(FNG TYPE)
−
40 to 85
−
55 to 150
150
Note 1: However, do not exceed 6.0 V.
Note 2: When mounted on a PCB (76.2
×
114.3
×
1.6 mm; Cu
=
30%; 35-
μ
m-thick; SEMI-compliant)
Note 3: Power dissipation is reduced by 1/R
th (j-a)
for each °C above 25°C ambient.
Operating Ranges
(unless otherwise specified, Ta
= −
40°C to 85°C)
Characteristics
Supply voltage
Output voltage
Symbol
V
DD
V
OUT
I
OUT
Output current
I
OH
I
OL
V
IH
Input voltage
V
IL
Clock frequency
LATCH
pulse width
Test Condition
⎯
Min
3
0.4
5
⎯
⎯
Typ.
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Max
5.5
4
40
−
5
Unit
V
V
mA/ch
mA
OUT
0
to OUT
7
OUT
0
to OUT
7
SERIAL-OUT
SERIAL-OUT
SERIAL-IN/CLOCK/
LATCH / ENABLE
Cascade connection
(Note 2)
(Note 2)
I
OUT
≥
20 mA
5 mA
≤
I
OUT
≤
20 mA
(Note 2)
(Note 2)
5
V
DD
0.3
×
V
DD
25
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0.7
×
V
DD
GND
⎯
V
f
CLK
t
wLAT
t
wCLK
t
wENA
t
SETUP1
t
SETUP2
MHz
ns
20
20
2
3
5
5
CLOCK pulse width
ENABLE pulse width
μ
s
Setup time
(Note 2)
5
5
⎯
ns
Hold time
Maximum clock rise time
Maximum clock fall time
t
HOLD1
t
HOLD2
t
r
t
f
Single operation
(Notes 1 and 2)
5
5
⎯
μ
s
Note 1: For cascade operation, the CLOCK waveform might become ambiguous, causing the t
r
and t
f
values to be
large. Then it may not be possible to meet the timing requirement for data transfer. Please consider the
timing carefully.
Note 2: Please see the timing waveform on page 9.
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2010-03-08
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