ispLSI 3192
®
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
High Density Programmable Logic
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— 192 I/O Pins
— 9000 PLD Gates
— 384 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
—
f
max
= 100 MHz Maximum Operating Frequency
—
t
pd
= 10 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— Supports ISP™ or ispJTAG™ Programming
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Mini-
mize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
0139/3192
Functional Block Diagram
ORP
F3
F2
ORP
ORP
ORP
Boundary
Scan
F1
F0
E3
E2
E1
E0
Global Routing Pool
D Q
ORP
A1
Array
D Q
D2
Twin
GLB
D1
D0
AND Array
D Q
ORP
D Q
A3
OR
Array
D Q
D Q
D Q
B0
B1
B2
B3
C0
C1
C2
C3
ORP
ORP
ORP
ORP
Description
The ispLSI 3192 is a High Density Programmable Logic
Device containing 384 Registers, 192 Universal I/O pins,
five Dedicated Clock Input Pins, twelve Output Routing
Pools (ORP), and a Global Routing Pool (GRP) which
allows complete inter-connectivity between all of these
elements. The ispLSI 3192 features 5-Volt in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3192 offers non-volatile reprogrammability of
the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3192 device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...F3.
There are a total of 24 of these Twin GLBs in the ispLSI
3192 device. Each Twin GLB has 24 inputs, a program-
mable AND array and two OR/Exclusive-OR Arrays, and
eight outputs which can be configured to be either com-
binatorial or registered. All Twin GLB inputs come from
the GRP.
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2002
3192_08
1
ORP
A2
ORP
A0
OR
D Q
D3
I/O 9
I/O 11
I/O 13
I/O 15
I/O 17
I/O 19
I/O 21
I/O 23
I/O 1
I/O 3
I/O 5
I/O 7
I/O 25
I/O 27
I/O 29
I/O 31
RESET
I/O 16
I/O 18
I/O 20
I/O 22
I/O 0
I/O 2
I/O 4
I/O 6
TOE
GOE0
I/O 8
I/O 10
I/O 12
I/O 14
I/O 24
I/O 26
I/O 28
I/O 30
Input Bus
GOE1
Megablock
Generic
Logic
Blocks
Output Routing Pool Output Routing Pool
A3
A0
A2
A1
B0
F3
Functional Block Diagram
I/O 33
I/O 35
I/O 37
I/O 39
I/O 32
I/O 34
I/O 36
I/O 38
I/O 190
I/O 188
I/O 186
I/O 184
I/O 182
I/O 180
I/O 178
I/O 176
I/O 174
I/O 172
I/O 170
I/O 168
I/O 166
I/O 164
I/O 162
I/O 160
I/O 191
I/O 189
I/O 187
I/O 185
I/O 183
I/O 181
I/O 179
I/O 177
I/O 175
I/O 173
I/O 171
I/O 169
I/O 167
I/O 165
I/O 163
I/O 161
B1
F2
I/O 41
I/O 43
I/O 45
I/O 47
I/O 40
I/O 42
I/O 44
I/O 46
Input Bus
B2
F1
Input Bus
I/O 49
I/O 51
I/O 53
I/O 55
I/O 48
I/O 50
I/O 52
I/O 54
Output Routing Pool Output Routing Pool
B3
F0
Figure 1. ispLSI 3192 Functional Block Diagram
Output Routing Pool Output Routing Pool
I/O 57
I/O 59
I/O 61
I/O 63
I/O 56
I/O 58
I/O 60
I/O 62
Global Routing Pool
(GRP)
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
2
C0
I/O 65
I/O 67
I/O 69
I/O 71
I/O 64
I/O 66
I/O 68
I/O 70
E3
I/O 158
I/O 156
I/O 154
I/O 152
I/O 159
I/O 157
I/O 155
I/O 153
C1
E2
I/O 73
I/O 75
I/O 77
I/O 79
I/O 72
I/O 74
I/O 76
I/O 78
I/O 150
I/O 148
I/O 146
I/O 144
I/O 151
I/O 149
I/O 147
I/O 145
Input Bus
Input Bus
C2
E1
I/O 81
I/O 83
I/O 85
I/O 87
I/O 80
I/O 82
I/O 84
I/O 86
I/O 142
I/O 140
I/O 138
I/O 136
I/O 143
I/O 141
I/O 139
I/O 137
C3
E0
Output Routing Pool Output Routing Pool
Output Routing Pool Output Routing Pool
I/O 89
I/O 91
I/O 93
I/O 95
I/O 88
I/O 90
I/O 92
I/O 94
I/O 134
I/O 132
I/O 130
I/O 128
I/O 135
I/O 133
I/O 131
I/O 129
Boundary
Scan
Y0
Y1
Y2
Y3
Y4
CLK 0
CLK 1
CLK 2
IOCLK 1
IOCLK 0
Output Routing Pool Output Routing Pool
D0
I/O 102
I/O 100
I/O 98
I/O 96
D1
I/O 110
I/O 108
I/O 106
I/O 104
Input Bus
D2
I/O 118
I/O 116
I/O 114
I/O 112
D3
I/O 126
I/O 124
I/O 122
I/O 120
BSCAN/ispEN
TCLK/SCLK
TMS/MODE
TRST
TDI/SDI
Specifications
ispLSI 3192
0139.3192.2.eps
TDO/SDO
I/O 103
I/O 101
I/O 99
I/O 97
I/O 111
I/O 109
I/O 107
I/O 105
I/O 119
I/O 117
I/O 115
I/O 113
I/O 127
I/O 125
I/O 123
I/O 121
Specifications
ispLSI 3192
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Description (Continued)
All local logic block outputs are brought back into the
GRP so they can be connected to the inputs of any other
logic block on the device. The device also has 192 I/O
cells, each of which is directly connected to an I/O pin.
Each I/O cell can be individually programmed to be a
combinatorial input, a registered input, a latched input, an
output or a bidirectional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
The 192 I/O Cells are grouped into six sets of 32 bits.
Each of these I/O groups is associated with a logic
Megablock through the use of the ORP. Each Megablock
is able to provide one Product Term Output Enable
(PTOE) signal which is globally distributed to all I/O cells.
That PTOE signal can be generated within any GLB in the
Megablock. Each I/O cell can select either a Global OE
or a PTOE.
Four Twin GLBs, 32 I/O Cells and two ORPs are con-
nected together to make a logic Megablock. The
Megablock is defined by the resources that it shares. The
outputs of the four Twin GLBs are connected to a set of
32 I/O cells by the two ORPs. The ispLSI 3192 device
contains six of these Megablocks.
The GRP has as its inputs the outputs from all of the Twin
GLBs and all of the inputs from the bidirectional I/O cells.
All of these signals are made available to the inputs of the
Twin GLBs. Delays through the GRP have been equal-
ized to minimize timing skew and logic glitching.
Clocks in the ispLSI 3192 device are provided through
five dedicated clock pins. The five pins provide three
clocks to the Twin GLBs and two clocks to the I/O cells.
The table below lists key attributes of the device along
with the number of resources available.
An additional feature of the ispLSI 3192 is the Boundary
Scan capability, which is composed of cells connected
between the on-chip system logic and the device's input
and output pins. All I/O pins have associated boundary
scan registers, with 3-state I/O using three boundary
scan registers and inputs using one.
The ispLSI 3192 supports all IEEE 1149.1 mandatory
instructions, which include BYPASS, EXTEST and
SAMPLE.
Key Attributes of the ispLSI 3192
Attribute
Twin GLBs
Registers
I/O Pins
Global Clocks
Global OE
Test OE
Quantity
24
384
192
5
2
1
Table - 003/3192
3
Specifications
ispLSI 3192
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Absolute Maximum Ratings
1
Supply Voltage V
cc
.................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to V
CC
+1.0V
Off-State Output Voltage Applied ..... -2.5 to V
CC
+1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T
J
) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Commercial
Industrial
T
A
= 0°C to +70°C
T
A
= -40°C to +85°C
MIN.
4.75
4.5
0
2.0
MAX.
5.25
5.5
0.8
V
CC
+1
UNITS
V
V
V
V
Table 2 - 0005/3192
V
CC
V
IL
V
IH
Capacitance (T
A
=25°C,f=1.0 MHz)
SYMBOL
PARAMETER
I/O Capacitance
Clock Capacitance
TYPICAL
10
15
UNITS
pf
pf
TEST CONDITIONS
V
CC
= 5.0V, V
I/O
= 2.0V
V
CC
= 5.0V, V
Y
= 2.0V
Table 2 - 0006/3192
C
1
C
2
Data Retention Specifications
PARAMETER
Data Retention
ispLSI Erase/Reprogram Cycles
MINIMUM
20
10000
MAXIMUM
–
–
UNITS
Years
Cycles
Table 2- 0008B
4
Specifications
ispLSI 3192
Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
≤
3ns 10% to 90%
1.5V
1.5V
See figure 2
Table 2 - 0003
Figure 2. Test Load
+ 5V
R1
Device
Output
R2
CL
*
Test
Point
3-state levels are measured 0.5V from steady-state
active level.
Output Load conditions (See figure 2)
*
CL includes Test Fixture and Probe Capacitance.
TEST CONDITION
A
B
Active High
Active Low
Active High to Z
at
V
OH
-0.5V
Active Low to Z
at
V
OL
+0.5V
R1
470Ω
∞
470Ω
∞
470Ω
R2
390Ω
390Ω
390Ω
390Ω
390Ω
CL
35pF
35pF
35pF
5pF
5pF
Table 2 - 0004A
0213A
C
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
Bscan/ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
CONDITION
I
OL
= 8 mA
I
OH
= -4 mA
0V
≤
V
IN
≤
V
IL
(Max.)
3.5V
≤
V
IN
≤
V
CC
0V
≤
V
IN
≤
V
IL
0V
≤
V
IN
≤
V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.0V, V
IH
= 3.0V Commercial
f
TOGGLE
= 1 MHz
Industrial
MIN.
–
2.4
–
–
–
–
–
–
–
TYP.
–
–
–
–
–
–
–
320
320
3
MAX. UNITS
0.4
–
-10
10
-150
-150
-200
–
–
V
V
µA
µA
µA
µA
mA
mA
mA
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2,4
Table 2 - 0007isp/3192
1. One output at a time for a maximum duration of one second. V
OUT
= 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using twelve 16-bit counters.
3. Typical values are at V
CC
= 5V and T
A
= 25°C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate
maximum I
CC
.
5
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