19-1531; Rev 3; 12/02
KIT
ATION
EVALU
E
BL
AVAILA
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
General Description
The MAX1290/MAX1292 low-power, 12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and
a high-speed, byte-wide parallel interface. The devices
operate with a single +5V analog supply and feature a
V
LOGIC
pin that allows them to interface directly with a
+2.7V to +5.5V digital supply.
Power consumption is only 10mW (V
DD
= V
LOGIC
) at a
400ksps max sampling rate. Two software-selectable
power-down modes enable the MAX1290/MAX1292 to
be shut down between conversions; accessing the par-
allel interface returns them to normal operation.
Powering down between conversions can cut supply
current to under 10µA at reduced sampling rates.
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1290 has
eight input channels and the MAX1292 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power consumption and space requirements.
The MAX1290/MAX1292 tri-states
INT
when
CS
goes
high. Refer to MAX1262/MAX1264 if tri-stating
INT
is not
desired.
The MAX1290 is available in a 28-pin QSOP package,
while the MAX1292 comes in a 24-pin QSOP. For pin-
compatible +3V, 12-bit versions, refer to the MAX1291/
MAX1293 data sheet.
o
12-Bit Resolution, ±0.5 LSB Linearity
o
+5V Single-Supply Operation
o
User-Adjustable Logic Level (+2.7V to +5.5V)
o
Internal +2.5V Reference
o
Software-Configurable Analog Input Multiplexer
8-Channel Single-Ended/
4-Channel Pseudo-Differential (MAX1290)
4-Channel Single-Ended/
2-Channel Pseudo-Differential (MAX1292)
o
Software-Configurable Unipolar/Bipolar Analog
Inputs
o
Low Current: 2.5mA (400ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)
o
Internal 6MHz Full-Power Bandwidth Track/Hold
o
Byte-Wide Parallel (8 + 4) Interface
o
Small Footprint: 28-Pin QSOP (MAX1290)
24-Pin QSOP (MAX1292)
Features
MAX1290/MAX1292
Pin Configurations
TOP VIEW
HBEN 1
D7 2
D6 3
D5 4
D4 5
D3/D11 6
D2/D10 7
D1/D9 8
D0/D8 9
INT 10
RD 11
WR 12
24 V
LOGIC
23 V
DD
22 REF
21 REFADJ
20 GND
Applications
Industrial Control Systems
Energy Management
Data-Acquisition Systems
Data Logging
Patient Monitoring
Touchscreens
MAX1292
19 COM
18 CH0
17 CH1
16 CH2
15 CH3
14 CS
13 CLK
Ordering Information
PART
MAX1290ACEI
MAX1290BCEI
MAX1290AEEI
MAX1290BEEI
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 QSOP
28 QSOP
28 QSOP
28 QSOP
INL
(LSB)
±0.5
±1
±0.5
±1
QSOP
Pin Configurations continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
Ordering Information continued at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
MAX1290/MAX1292
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ..............................................................-0.3V to +6V
V
LOGIC
to GND.........................................................-0.3V to +6V
CH0–CH7, COM to GND ............................-0.3V to (V
DD
+ 0.3V)
REF, REFADJ to GND.................................-0.3V to (V
DD
+ 0.3V)
Digital Inputs to GND ...............................................-0.3V to +6V
Digital Outputs (D0–D11,
INT)
to GND ........................................... -0.3V to (V
LOGIC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
24-Pin QSOP (derate 9.5mW/°C above +70°C).........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C).......667mW
Operating Temperature Ranges
MAX1290_C_ _/MAX1292_C_ _ ....................... 0°C to +70°C
MAX1290_E_ _/MAX1292_E_ _ .....................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= V
LOGIC
= +5V ±10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 7.6MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
(Note 1)
Resolution
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
Gain Error (Note 3)
Gain Temperature Coefficient
Channel-to-Channel Offset
Matching
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
(including 5th-order harmonic)
Spurious-Free Dynamic Range
Intermodulation Distortion
Channel-to-Channel Crosstalk
Full-Linear Bandwidth
Full-Power Bandwidth
CONVERSION RATE
External clock mode
Conversion Time (Note 5)
T/H Acquisition Time
Aperture Delay
Aperture Jitter
External Clock Frequency
Duty Cycle
2
f
CLK
t
CONV
t
ACQ
External acquisition or external clock mode
External acquisition or external clock mode
Internal acquisition/internal clock mode
0.1
30
25
<50
<200
7.6
70
External acquisition/internal clock mode
Internal acquisition/internal clock mode
2.1
2.5
3.2
3.0
3.6
3.5
4
400
ns
ns
ps
MHz
%
µs
SINAD
THD
SFDR
IMD
f
IN1
= 49kHz, f
IN2
= 52kHz
f
IN
= 175kHz, V
IN
= 2.5V
P-P
(Note 4)
SINAD > 68dB
-3dB rolloff
80
76
-78
350
6
67
±2
±0.2
RES
INL
DNL
MAX129_A
MAX129_B
No missing codes over temperature
12
±0.5
±1
±1
±4
±4
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS
(f
IN(sine wave)
= 50kHz, V
IN
= 2.5V
P-P
, 400ksps, external f
CLK
= 7.6MHz, bipolar input mode)
70
-80
dB
dB
dB
dB
dB
kHz
MHz
_______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= V
LOGIC
= +5V ±10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 7.6MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
ANALOG INPUTS
Analog Input Voltage Range
Single Ended and Differential
(Note 6)
Multiplexer Leakage Current
Input Capacitance
INTERNAL REFERENCE
REF Output Voltage
REF Short-Circuit Current
REF Temperature Coefficient
REFADJ Input Range
REFADJ High Threshold
Load Regulation (Note 7)
Capacitive Bypass at REFADJ
Capacitive Bypass at REF
EXTERNAL REFERENCE AT REF
REF Input Voltage Range
Shutdown REF Input Current
DIGITAL INPUTS AND OUTPUTS
Input Voltage High
Input Voltage Low
Input Hysteresis
Input Leakage Current
Input Capacitance
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
V
IH
V
IL
V
HYS
I
IN
C
IN
V
OL
V
OH
I
LEAKAGE
C
OUT
I
SINK
= 1.6mA
I
SOURCE
= 1mA
CS
= V
DD
CS
= V
DD
V
LOGIC
- 0.5
±0.1
15
±1
V
IN
= 0 or V
DD
200
±0.1
15
0.4
±1
V
LOGIC
= 4.5V
V
LOGIC
= 2.7V
4.0
2.0
0.8
V
V
V
mV
µA
pF
V
V
µA
pF
V
REF
I
REF
V
REF
= 2.5V, f
SAMPLE
= 400ksps
Shutdown mode
1.0
200
V
DD
+
50mV
300
2
V
µA
4.7
TC
REF
For small adjustments
To power down the internal reference
0 to 0.5mA output load
V
DD
- 1
0.2
0.01
1
10
2.49
2.5
15
±20
±100
2.51
V
mA
ppm/°C
mV
V
mV/mA
µF
µF
C
IN
Unipolar, V
COM
= 0
V
IN
Bipolar, V
COM
= V
REF
/ 2
On/off-leakage current, V
IN
= 0 or V
DD
-V
REF
/2
±0.01
12
+V
REF
/2
±1
µA
pF
0
V
REF
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1290/MAX1292
_______________________________________________________________________________________
3
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
MAX1290/MAX1292
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= V
LOGIC
= +5V ±10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 7.6MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
V
DD
V
LOGIC
Operating mode,
f
SAMPLE
= 400ksps
Positive Supply Current
I
DD
Standby mode
Operating mode,
Shutdown mode
V
LOGIC
Current
Power-Supply Rejection
I
LOGIC
PSR
C
L
= 20pF
f
SAMPLE
= 400ksps
Nonconverting
2
±0.3
Internal reference
External reference
Internal reference
External reference
4.5
2.7
2.9
2.5
1.0
0.5
2
5.5
V
DD
+
0.3
3.4
2.9
1.2
0.8
10
200
10
±0.9
µA
µA
mV
mA
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
= +5V ±10%, full-scale input
TIMING CHARACTERISTICS
(V
DD
= V
LOGIC
= +5V ±10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 7.6MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
CLK Period
CLK Pulse Width High
CLK Pulse Width Low
Data Valid to
WR
Rise Time
WR
Rise to Data Valid Hold Time
WR
to CLK Fall Setup Time
CLK Fall to
WR
Hold Time
CS
to CLK or
WR
Setup Time
CLK or
WR
to
CS
Hold Time
CS
Pulse Width
WR
Pulse Width (Note 8)
SYMBOL
t
CP
t
CH
t
CL
t
DS
t
DH
t
CWS
t
CWH
t
CSWS
t
CSWH
t
CS
t
WR
CONDITIONS
MIN
132
40
40
40
0
40
40
60
0
100
60
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
_______________________________________________________________________________________
400ksps, +5V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS (continued)
(V
DD
= V
LOGIC
= +5V ±10%, COM = GND, REFADJ = V
DD
, V
REF
= +2.5V, 4.7µF capacitor at REF pin, f
CLK
= 7.6MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
CS
Rise to Output Disable
RD
Rise to Output Disable
RD
Fall to Output Data Valid
HBEN Rise to Output Data Valid
HBEN Fall to Output Data Valid
RD
Fall to
INT
High Delay
CS
Fall to Output Data Valid
SYMBOL
t
TC
t
TR
t
DO
t
DO1
t
DO1
t
INT1
t
DO2
CONDITIONS
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
C
LOAD
= 20pF, Figure 1
MIN
10
10
10
10
10
TYP
MAX
60
40
50
50
80
50
100
UNITS
ns
ns
ns
ns
ns
ns
ns
MAX1290/MAX1292
Note 1:
Tested at V
DD
= +5V, COM = GND, = 0, unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3:
Offset nulled.
Note 4:
On channel is grounded; sine wave applied to off channels.
Note 5:
Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6:
Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V
DD
.
Note 7:
External load should not change during conversion for specified accuracy.
Note 8:
When bit 5 is set low for internal acquisition,
WR
must not return low until after the first falling clock edge of the conversion.
V
LOGIC
3kΩ
DOUT
3kΩ
C
LOAD
20pF
DOUT
C
LOAD
20pF
a)
HIGH-Z TO V
OH
AND V
OL
TO V
OH
b)
HIGH-Z TO V
OL
AND V
OH
TO V
OL
Figure 1. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
5
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
