EVALUATION KIT AVAILABLE
MAX77826
Power Management IC
General Description
The MAX77826 is a subpower management IC for the
latest 3G/4G smartphones and tablets. The MAX77826
contains a high-efficiency BUCK regulator, a BUCK
BOOST regulator and 15 LDOs to power up peripherals.
The MAX77826 also provides power on/off control logic
and an I
2
C serial interface to program individual regulator
output voltages and on/off control for complete flexibility.
The linear regulators support a remote cap feature and
provide greater than 70dB PSRR and less than 45µV
RMS
noise.
The MAX77826 features I
2
C-compatible, 2-wire serial
interface that comprises a bidirectional serial data line
(SDA) and a serial clock line (SCL). The MAX77826 sup-
ports SCL clock rates up to 3.4MHz.
Benefits and Features
Applications
●
GSM, GPRS, EDGE, CDMA WCDMA, and LTE
Smartphones and Tablets
Ordering Information
appears at end of data sheet.
●
Compact Total Solution Size Allows More Peripheral
Devices in Smartphones and Tablets
•
3A High-Efficiency BUCK Regulator
• DVS (Dynamic Voltage Scaling) Through HS I
2
C
• ±1% (typ) Output Voltage DC Accuracy
• Low Power Mode
• 2A BUCK BOOST Regulator
• 15 Linear Regulators with Remote Cap
• 3 NMOS LDOs (V
OUT
Range: 0.6V to 2.1875V
with 12.5mV Step)
• 1 x 150mA
• 1 x 450mA
• 1 x 600mA
• 6 PMOSLV LDOs (V
OUT
Range: 0.8V to 3.975V
with 25mV Step)
• 3 x 150mA
• 3 x 300mA
• 6 PMOSLS LDOs (V
OUT
Range: 0.8V to 3.975V
with 25mV Step)
• 3 x 150mA
• 3 x 300mA
• ±1.5% Typical Output Voltage DC Accuracy
• 70dB PSRR at 1kHz
• Low Power Mode with 2µA (typ) for all LDOs
●
Simple Management of Power-Up/Down Sequence,
Output Voltage Setting, and Fault Detection
• High-Speed (Up to 3.4MHz) I
2
C Serial Interface
19-6893; Rev 1; 7/15
MAX77826
Power Management IC
Absolute Maximum Ratings
SYS, V
IO
, INL1, INL2, INL3,
INL4, INL5 to GND ...........................................-0.3V to +6.0V
INB to PGNDB......................................................-0.3V to +6.0V
INBB, OUTBB to PGNDBB ..................................-0.3V to +6.0V
PGNDB, PGNDBB to GND ..................................-0.3V to +0.3V
IRQB, CE, SDA, SCL to GND ................. -0.3V to (V
VIO
+ 0.3V)
FB_B, ENBB, ENB, ENL12,
REFBYP to GND ................................ -0.3V to (V
SYS
+ 0.3V)
FB_BB to PGNDBB ............................-0.3V to (V
OUTBB
+ 0.3V)
LXB to PGNDB ........................................ -0.3V to (V
INB
+ 0.3V)
LXBB1 to PGNDBB ............................... -0.3V to (V
INBB
+ 0.3V)
LXBB2 to PGNDBB ............................-0.3V to (V
OUTBB
+ 0.3V)
LDO1, LDO2 to GND ............................. -0.3V to (V
INL1
+ 0.3V)
LDO3 to GND ......................................... -0.3V to (V
INL2
+ 0.3V)
LDO4, LDO5, LDO6, LDO7, LDO8,
LDO9 to GND ..................................... -0.3V to (V
INL3
+ 0.3V)
LDO10, LDO11 to GND .......................... -0.3V to (V
INL4
+ 0.3V)
LDO12, LDO13, LDO14,
LDO15 to GND ................................... -0.3V to (V
INL5
+ 0.3V)
LXB Continuous RMS Current (Note 1) ..................................3A
LXBB1/LXBB2 Continuous RMS Current (Note 1) ..............3.3A
Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -65°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
Note 1:
LX_ node has internal clamp diodes to PGND_ and INB_. Applications that give forward bias to these diodes should ensure
that the total power loss does not exceed IC’s package power dissipation limits.
Package Thermal Characteristics
(Note 2)
WLP
Junction-to-Ambient Thermal Resistance (θ
JA
) ..........37°C/W
Note 2:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
General Electrical Characteristics
(V
SYS
= V
IN_
= +3.7V, V
IO
= 1.8V, T
A
= -40°C to +85°C, unless otherwise noted.)
VPARAMETER
Shutdown Supply Current
Standby Current
Shutdown V
IO
Current
No Load Supply Current 1
No Load Supply Current 2
No Load Supply Current 3
V
SYS
UNDERVOLTAGE LOCKOUT
V
SYS
Undervoltage Lockout
Threshold
REFERENCE
REFBYP Output Voltage
REFBYP Supply Rejection
2.7V ≤ V
SYS
≤ 5.5V
0.786
0.80
0.2
0.814
V
mV/V
V
UVLO_R
V
UVLO_F
V
SYS
rising
V
SYS
falling (default)
2.375
2.50
2.05
2.625
V
SYMBOL
I
SHDN_SYS
I
Q_SYS
I
SHDN_VIO
I
NO_LOAD1
I
NO_LOAD2
I
NO_LOAD3
CE = low
CE = high and all regulators are off
All regulators are off
BUCK is on in normal mode
(no switching)
BUCK and BUCK BOOST are on in
normal mode (no switching)
All regulators are on in normal
mode (no switching)
CONDITIONS
MIN
TYP
2.5
35
0
60
120
400
700
MAX
10
UNITS
µA
µA
µA
µA
µA
µA
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MAX77826
Power Management IC
General Electrical Characteristics (continued)
(V
SYS
= V
IN_
= +3.7V, V
IO
= 1.8V, T
A
= -40°C to +85°C, unless otherwise noted.)
PARAMETER
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Interrupt at +120°C
Thermal Interrupt at +140°C
LOGIC AND CONTROL INPUTS
Input Low Level
V
IL
ENB, ENBB,
ENL12
CE
ENB, ENBB,
ENL12
CE
CE
(0V < V
IO
< 1.8V)
I
SINK
= 1mA
V
IO
= 5.5V
T
A
= +25°C
T
A
= +85°C
400
-1
0.1
800
1600
V
SYS
≤ 4.5V
T
A
= +25°C
T
A
= +25°C
V
SYS
≤ 4.5V
T
A
= 25°C
T
A
= +25°C
T
A
= +25°C
T
A
= +85°C
1.2
0.7 x V
VIO
-1
0.1
0.4
+1
+1
0.4
0.3 x V
VIO
V
V
T
SHDN
T
120
T
140
T
J
rising, 15°C hysteresis
T
J
rising, 15°C hysteresis
T
J
rising, 15°C hysteresis
+165
+120
+140
°C
°C
°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Level
V
IH
Logic Input Leakage Current
IRQB Output Low Voltage
IRQB Output High Leakage
I
LEAK
V
OL
I
OZH
µA
V
µA
INTERNAL PULLDOWN RESISTANCE
ENB, ENBB, ENL12
R
PD
Pulldown resistor to GND
kΩ
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MAX77826
Power Management IC
I
2
C Electrical Characteristics
(V
SYS
= V
IN_
= +3.7V, V
IO
= 1.8V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
POWER SUPPLY
VIO Voltage
SDA AND SCL I/O STAGES
SCL, SDA Input High Voltage
SCL, SDA Input Low Voltage
SCL, SDA Input Hysteresis
SCL, SDA Input Current
SDA Output Low Voltage
SCL, SDA Pin Capacitance
Output Fall Time from
V
IO
to 0.3 x V
IO
Clock Frequency
Hold Time (REPEATED) START
Condition
CLK Low Period
CLK High Period
Setup Time REPEATED START
Condition
DATA Hold Time
DATA Setup Time
Setup Time for STOP Condition
Bus-Free Time Between
STOP and START
Capacitive Load for
Each Bus Line
Maximum Pulse Width of
Spikes That Must Be
Suppressed by the Input Filter
V
IH
V
IL
V
HYS
I
I
V
OL
C
I
t
OF
V
IO
= 3.7V
I
SINK
= 20mA
10
120
-10
0.05 x V
VIO
+10
0.4
0.7 x V
VIO
0.3 x V
VIO
V
V
V
µA
V
pF
ns
V
VIO
1.7
3.6
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
2
C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST, AND FAST MODE PLUS) (Note 3)
f
SCL
t
HD;STA
t
LOW
t
HIGH
t
SU;STA
t
HD:DAT
t
SU;DAT
t
SU;STO
t
BUF
C
B
50
0.26
0.5
0.26
0.26
0
50
0.26
0.5
550
1000
kHz
µs
µs
µs
µs
µs
ns
µs
µs
pF
ns
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Maxim Integrated
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MAX77826
Power Management IC
I
2
C Electrical Characteristics (continued)
(V
SYS
= V
IN_
= +3.7V, V
IO
= 1.8V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
C
B
= 100pF
MIN
TYP
MAX
3.4
160
160
160
60
10
35
T
A
= +25°C
10
40
20
160
160
320
120
10
75
80
MIN
C
B
= 400pF
TYP
MAX
1.7
UNITS
I
2
C-COMPATIBLE INTERFACE TIMING (HS MODE)
Clock Frequency
Set-Up Time REPEATED
START Condition
Hold Time (REPEATED)
START Condition
CLK Low Period
CLK High Period
DATA Setup time
DATA Hold Time
SCL Rise Time
(Note 3)
Rise Time of SCL Signal
After a REPEATED
START Condition and
After an Acknowledge Bit
(Note 3)
SCL Fall Time
(Note 3)
SDA Rise Time
(Note 3)
SDA Fall Time
(Note 3)
Set-Up Time for STOP
Condition
Capacitive Load for Each
Bus Line
Maximum Pulse Width
of Spikes That Must Be
Suppressed by the Input
Filter
f
SCL
t
SU;STA
t
HD;STA
t
LOW
t
HIGH
t
SU:DAT
t
HD:DAT
t
RCL
MHz
ns
ns
ns
ns
ns
ns
ns
t
rCL1
T
A
= +25°C
10
80
20
160
ns
t
fCL
t
rDA
t
fDA
t
SU;STO
C
B
T
A
= +25°C
T
A
= +25°C
T
A
= +25°C
10
40
80
80
20
80
160
160
ns
ns
ns
ns
160
100
160
400
pF
10
10
ns
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