Differential-to-LVDS/0.7V Differential
PCI Express™ Jitter Attenuator
Data Sheet
8741004I
General Description
The 8741004I is a high performance Differential-to-LVDS/0.7V
Differential Jitter Attenuator designed for use in PCI Express™
systems. In some PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In these
systems, a jitter attenuator may be required to attenuate high
frequency random and deterministic jitter components from the PLL
synthesizer and from the system board. The 8741004I has 3 PLL
bandwidth modes: 200kHz, 600kHz and 2MHz. The 200kHz mode
will provide maximum jitter attenuation, but with higher PLL tracking
skew and spread spectrum modulation from the motherboard
synthesizer may be attenuated. The 600kHz provides an
intermediate bandwidth that can easily track triangular spread
profiles, while providing good jitter attenuation. The 2MHz bandwidth
provides the best tracking skew and will pass most spread profiles,
but the jitter attenuation will not be as good as the lower bandwidth
modes. Because some 2.5Gb serdes have x20 multipliers while
others have x25 multipliers, the 8741004I can be set for 1:1 mode or
5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the
F_SEL pins.
The 8741004I uses IDT’s 3
rd
Generation FemtoClock™
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI Express
add-in cards.
Features
•
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•
•
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Two LVDS and two 0.7V differential output pairs
Bank A has two LVDS output pairs and
Bank B has two 0.7V differential output pairs
One differential clock input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 160MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum)
Full 3.3V operating supply
Three bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
-40°C to 85°C ambient operating temperature
Available in lead-free packages
Pin Assignment
nQA1
QA1
V
DDO
QA0
nQA0
MR
BW_SEL
nc
V
DDA
F_SELA
V
DD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQB1
QB1
V
DDO
QB0
nQB0
IREF
F_SELB
OEB
GND
GND
nCLK
CLK
PLL Bandwidth
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~600kHz (default)
1 = PLL Bandwidth: ~2MHz
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A January 27, 2016
8741004I Data Sheet
Block Diagram
OEA
Pullup
F_SELA
Pulldown
QA0
BW_SEL
Float
0 = ~200kHz
Float = ~400kHz
1 = ~800kHz
F_SELA
0 ÷5
(default)
1 ÷4
nQA0
QA1
CLK
Pulldown
nCLK
Pullup
Phase
Detector
VCO
490 - 640 MHz
nQA1
QB0
M = ÷5 (fixed)
F_SELB
0 ÷5
(default)
1 ÷4
nQB0
QB1
nQB1
F_SELB
Pulldown
MR
Pulldown
IREF
Pullup
OEB
©2016 Integrated Device Technology, Inc
2
Revision A January 27, 2016
8741004I Data Sheet
Table 1. Pin Descriptions
Number
1, 2
3, 22
4, 5
Name
nQA1, QA1
V
DDO
QA0, nQA0
Output
Power
Output
Type
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q[Ax:Bx] to go LOW and the inverted outputs
nQ[Ax:Bx] to go HIGH. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B.
No connect.
Analog supply pin.
Pulldown
Frequency select pins for QAx/nQAx outputs.
LVCMOS/LVTTL interface levels. See Table 3C.
Core supply pin.
Pullup
Pulldown
Pullup
Output enable for QAx pins. When HIGH, QAx/nQAx outputs are enabled.
When LOW, the QAx/nQAx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply ground.
Pullup
Output enable for QBx pins. When HIGH, QBx/nQBx outputs are enabled.
When LOW, the QBx/nQBx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
Frequency select pins for QBx/nQBx outputs.
LVCMOS/LVTTL interface levels. See Table 3C.
A fixed precision resistor (RREF = 475
) from this pin to ground provides a
reference current used for differential current-mode QB0/nQB0 clock outputs.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
6
MR
Input
Pulldown
7
8
9
10
11
12
13
14
15, 16
17
BW_SEL
nc
V
DDA
F_SELA
V
DD
OEA
CLK
nCLK
GND
OEB
Input
Unused
Power
Input
Power
Input
Input
Input
Power
Input
Pullup/
Pulldown
18
19
20, 21
23, 24
F_SELB
IREF
nQB0, QB0
QB1, nQB1
Input
Input
Output
Output
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc
3
Revision A January 27, 2016
8741004I Data Sheet
Function Tables
Table 3A. Output Enable Function Table
Inputs
OEA
0
1
OEB
0
1
Outputs
QA[0:1]/nQA[0:1]
Hi-Z
Enabled
QB[0:1]/nQB[0:1]
Hi-Z
Enabled
Table 3B. PLL Bandwidth Function Table
Input
BW_SEL
0
Float
1
PLL Bandwidth
~200kHz
~600kHz (default)
~2MHz
Table 3C. Frequency Select Table
Inputs
F_SEL[A, B]
0
1
Divider
÷5 (default)
÷4
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
32.1C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.12
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
45
12
80
Units
V
V
V
mA
mA
mA
©2016 Integrated Device Technology, Inc
4
Revision A January 27, 2016
8741004I Data Sheet
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
Parameter
OEA, OEB, MR,
F_SELA, F_SELB
BW_SEL
OEA, OEB, MR,
F_SELA, F_SELB
BW_SEL
V
IM
I
IH
Input Mid Voltage
BW_SEL
F_SELA, F_SELB,
MR, BW_SEL
OEA, OEB
MR,
F_SELA, F_SELB,
OEA, OEB, BW_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
V
DD
– 0.3
-0.3
-0.3
V
DD
/2 – 0.1
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
+0.3
V
DD
/2 + 0.1
150
5
Units
V
V
V
V
V
µA
µA
µA
µA
V
IH
Input High Voltage
V
IL
Input Low Voltage
Input High Current
I
IL
Input Low Current
Table 4C. Differential DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
CLK
Input High Current
nCLK
CLK
I
IL
Input Low Current
nCLK
V
PP
V
CMR
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, NOTE 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V,
V
IN
= 0V
V
DD
= 3.465V,
V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4D. LVDS DC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.2
1.35
Test Conditions
Minimum
290
Typical
390
Maximum
490
50
1.5
50
Units
mV
mV
V
mV
©2016 Integrated Device Technology, Inc
5
Revision A January 27, 2016
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