The AS7C31025C is 3V a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x
8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10 ns with output enable access times (t
OE
) of 5 ns are ideal for high-performance
applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems.
When CE is high the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data
on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention,
external devices should drive I/O pins only after outputs have been disabled with
output enable (
OE
) or write enable
(WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins
with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output
drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025C is packaged in common
industry standard packages.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–
–55
–55
–
Max
+4.6
V
CC
+ 0.5
1.25
+125
+125
50
Unit
V
V
W
o
C
o
C
mA
NOTE: Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
L
L
WE
X
H
H
L
OE
X
H
L
X
Data
High Z
High Z
D
OUT
D
IN
Mode
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (I
CC
)
Key: X = don’t care, L = low, H = high.
9/20/06, v. 1.0
Alliance Memory
P. 2 of 9
AS7C31025C
®
Recommended operating conditions
Parameter
Supply voltage
Input voltage
Ambient operating temperature (Industrial)
V
IL
min = –2.0V for pulse width less than 5ns, once per cycle.
V
IH
min = –V
CC
+ 2.0V for pulse width less than 5ns, once per cycle.
Symbol
V
CC
V
IH
V
IL
T
A
Min
3.0
2.0
–0.5
–40
Nominal
3.3
–
–
–
Max
3.6
V
CC
+ 0.3
0.8
85
Unit
V
V
V
o
C
DC operating characteristics (over the operating range)
1
AS7C31025C-10
Parameter
Input leakage current
Output leakage current
Sym
|
I
LI
|
|
I
LO
|
Test conditions
V
CC
= Max, V
IN
= GND to V
CC
V
CC
= Max, CE = V
IH
,
V
out
= GND to V
CC
V
CC
= Max
CE
≤
V
IL
, f = f
Max
,
I
OUT
= 0 mA
V
CC
= Max
CE
≥
V
IH
, f = f
Max
V
CC
= Max, CE
≥
V
CC
–0.2 V,
V
IN
≤
0.2 V or V
IN
≥
V
CC
–0.2 V,
f=0
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
Min
–
–
Max
5
5
Unit
μA
μA
Operating power supply current
I
CC
–
150
mA
I
SB
Standby power supply current
1
I
SB1
V
OL
V
OH
–
50
mA
–
–
2.4
10
0.4
–
mA
V
V
Output voltage
Capacitance (
f = 1 MHz, T
a
= 25
o
C, V
CC
= NOMINAL
)
2
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
A, CE, WE, OE
I/O
Test conditions
V
IN
= 3dV
V
OUT
= 3dV
Max
6
7
Unit
pF
pF
Note:
1. This parameter is guaranteed by device characterization, but is not production tested.
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]
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