PCA9306
Dual Bidirectional I
2
C-bus
and SMBus Voltage-Level
Translator
The PCA9306 is a dual bidirectional I
2
C−bus and SMBus
voltage−level translator with an enable (EN) input.
Features
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MARKING
DIAGRAMS
8
TSSOP−8
DT SUFFIX
CASE 948AL
1
8
US8
US SUFFIX
CASE 493
1
UQFN8
MU SUFFIX
CASE 523AN
1
AQ MG
AAF
YWW-
AG
•
2−bit Bidirectional Translator for SDA and SCL Lines in
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Mixed−Mode I
2
C−Bus Applications
Standard−Mode, Fast−Mode, and Fast−Mode Plus I
2
C−Bus and
SMBus Compatible
Less Than 1.5 ns Maximum Propagation Delay to Accommodate
Standard−Mode and Fast−Mode I
2
C−Bus Devices and Multiple
Masters
Allows Voltage Level Translation Between:
♦
1.0 V V
ref(1)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
bias(ref)(2)
♦
1.2 V V
ref(1)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
bias(ref)(2)
♦
1.8 V V
ref(1)
and 3.3 V or 5 V V
bias(ref)(2)
♦
2.5 V V
ref(1)
and 5 V V
bias(ref)(2)
♦
3.3 V V
ref(1)
and 5 V V
bias(ref)(2)
Provides Bidirectional Voltage Translation With No Direction Pin
Low 3.5
W
ON−State Connection Between Input and Output Ports
Provides Less Signal Distortion
Open−Drain I
2
C−Bus I/O Ports (SCL1, SDA1, SCL2 and SDA2)
5 V Tolerant I
2
C−Bus I/O Ports to Support Mixed−Mode Signal
Operation
High−Impedance SCL1, SDA1, SCL2 and SDA2 Pins for
EN = LOW
Lock−Up Free Operation
Flow Through Pinout for Ease of Printed−Circuit Board Trace
Routing
Packages Offered:
♦
TSSOP−8, US8, UQFN8, UDFN8
ESD Performance: 4000 V Human Body Model,
400 V Machine Model
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
AK MG
G
1
8
UDFN8
1.45 x 1.0
CASE 517BZ
PM
1
AAF, AK, AQ, P
A
Y
WW
M
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Date Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 6
Publication Order Number:
PCA9306/D
PCA9306
Function Description
The PCA9306 is a dual bidirectional I
2
C−bus and SMBus
voltage−level translator with an enable (EN) input, and is
operational from 1.0 V to 3.6 V (V
ref(1)
) and 1.8 V to 5.5 V
(V
bias(ref)(2)
).
The PCA9306 allows bidirectional voltage translations
between 1.0 V and 5 V without the use of a direction pin. The
low ON−state resistance (R
on
) of the switch allows
connections to be made with minimal propagation delay.
When EN is HIGH, the translator switch is on, and the SCL1
and SDA1 I/O are connected to the SCL2 and SDA2 I/O,
respectively, allowing bidirectional data flow between
ports. When EN is LOW, the translator switch is off, and a
high−impedance state exists between ports.
The PCA9306 is not a bus buffer that provides both level
translation and physical capacitance isolation to either side
of the bus when both sides are connected. The PCA9306
only isolates both sides when the device is disabled and
provides voltage level translation when active.
The PCA9306 can be used to run two buses, one at
400 kHz operating frequency and the other at 100 kHz
operating frequency. If the two buses are operating at
different frequencies, the 100 kHz bus must be isolated
when the 400 kHz operation of the other bus is required. If
the master is running at 400 kHz, the maximum system
operating frequency may be less than 400 kHz because of
the delays added by the translator.
As with the standard I
2
C−bus system, pull−up resistors are
required to provide the logic HIGH levels on the translator’s
bus. The PCA9306 has a standard open−collector
configuration of the I
2
C−bus. The size of these pull−up
resistors depends on the system, but each side of the
translator must have a pull−up resistor. The device is
designed to work with Standard−mode, Fast−mode and Fast
mode Plus I
2
C−bus devices in addition to SMBus devices.
The maximum frequency is dependent on the RC time
constant, but generally supports > 2 MHz.
When the SDA1 or SDA2 port is LOW, the clamp is in the
ON−state and a low resistance connection exists between the
SDA1 and SDA2 ports. Assuming the higher voltage is on
the SDA2 port, when the SDA2 port is HIGH, the voltage on
the SDA1 port is limited to the voltage set by VREF1. When
the SDA1 port is HIGH, the SDA2 port is pulled to the drain
pull−up supply voltage (V
pu(D)
) by the pull−up resistors.
This functionality allows a seamless translation between
higher and lower voltages selected by the user without the
need for directional control. The SCL1/SCL2 channel also
functions as the SDA1/SDA2 channel.
All channels have the same electrical characteristics and
there is minimal deviation from one output to another in
voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication
of the switch is symmetrical. The translator provides
excellent ESD protection to lower voltage devices, and at the
same time protects less ESD−resistant devices.
FUNCTIONAL DIAGRAM
Figure 1. Logic Diagram
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2
PCA9306
PIN ASSIGNMENTS
Figure 2. TSSOP−8 / US8 Pinouts
Figure 3. UQFN8 Pinout (Top Thru View)
Figure 4. UDFN8 Pinout (Top Thru View)
Table 1. PIN DESCRIPTION
Pin
GND
VREF1
SCL1
SDA1
SDA2
SCL2
VREF2
EN
Ground
Low−voltage side reference supply voltage for SCL1 and SDA1
Serial clock, low−voltage side; connect to VREF1 through a pull−up resistor
Serial data, low−voltage side; connect to VREF1 through a pull−up resistor
Serial data, high−voltage side; connect to VREF2 through a pull−up resistor
Serial clock, high−voltage side; connect to VREF2 through a pull−up resistor
High−voltage side reference supply voltage for SCL2 and SDA2
Switch enable input; connect to VREF2 and pull−up through a high resistor
Description
Table 2. FUNCTION TABLE
Input EN
(Note 1)
Low
High
Disconnect
SCL1 = SCL2; SDA1 = SDA2
Function
1. EN is controlled by the V
bias(ref)(2)
logic levels and should be at least 1 V higher than V
ref(1)
for best translator operation.
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3
PCA9306
Table 3. MAXIMUM RATINGS
Symbol
V
ref(1)
V
bias(ref)(2)
V
IN
V
I/O
I
CH
I
IK
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
Reference Voltage (Note 2)
Reference Bias Voltage (Note 3)
Input Voltage
Input / Output Pin Voltage
DC Channel Current
DC Input Diode Current V
IN
< GND
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
Power Dissipation in Still Air at 85°C
Moisture Sensitivity
Flammability Rating Oxygen Index: 28 to 34
ESD Withstand Voltage Human Body Mode (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
Latchup Performance Above V
CC
and Below GND at 125
°C
(Note 6)
Parameter
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
128
−50
−65 to +150
T
L
= 260
T
J
= 150
q
JA
= 150
P
D
= 833
Level 1
UL 94 V−0 @ 0.125 in
> 4000
> 400
N/A
±100
V
Unit
V
V
V
V
mA
mA
°C
°C
°C
°C/W
mW
I
LATCHUP
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
3. Tested to EIA / JESD22−A114−A.
4. Tested to EIA / JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA / JESD78.
Table 4. RECOMMENDED OPERATING CONDITIONS
Symbol
V
ref(1)
V
bias(ref)(2)
V
I/O
V
I(EN)
I
sw(pass)
T
A
Reference Voltage (1) (Note 7)
Reference Bias Voltage (2) (Note 7)
Input / Output Pin Voltage SCL1, SDA1, SCL2, SDA2
Control Pin Input Voltage EN
Pass Switch Current
Operating Free−Air Temperature
Parameter
VREF1
VREF2
Min
0
0
0
0
0
−55
Max
5.5
5.5
5.5
5.5
64
+125
Unit
V
V
V
V
mA
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. V
(ref)(1)
≤
V
bias(ref)(2)
−1 V for best results in level shifting applications.
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PCA9306
Table 5. DC ELECTRICAL CHARACTERISTICS
T
A
= −555C to +1255C
Symbol
V
IK
I
IH
C
i(EN)
C
i/O(off)
C
i/O(on)
R
ON
Parameter
Input Clamping Voltage
High−Level Input Current
EN Pin Input Capacitance
OFF−State I/O Pin Capacitance
SCLn, SDAn
ON−State I/O Pin Capacitance
SCLn, SDAn
ON−State Resistance
(2)(3)
SCLn, SDAn
Conditions
I
I
=
−18
mA; V
I(EN)
= 0 V
V
I
= 5 V; V
I(EN)
= 0 V
V
I
= 3 V or 0 V
V
O
= 3 V or 0 V; V
I(EN)
= 0 V
V
O
= 3 V or 0 V;
V
I(EN)
= 3 V
V
I
= 0 V; I
O
= 64 mA
V
I(EN)
= 4.5 V
V
I(EN)
= 3 V
V
I(EN)
= 2.3 V
V
I(EN)
= 1.5 V
V
I
= 2.4 V; I
O
= 15 mA
V
I(EN)
= 4.5 V
V
I(EN)
= 3 V
V
I
= 1.7 V; I
O
= 15 mA
V
I(EN)
= 2.3 V
7.1
4
6
Min
Typ
(Note 8)
Max
−1.2
5
Unit
V
mA
pF
pF
pF
9.3
2.4
3.0
3.8
9.0
4.8
46
40
12.5
W
5.0
6.0
8.0
20
7.5
80
80
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. All typical values are at T
A
= 25°C.
9. Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch.
ON−state resistance is determined by the lowest voltage of the two terminals.
10. Guaranteed by design.
Table 6. AC ELECTRICAL CHARACTERISTICS
(Translating Down) − Values Guaranteed by Design
Load
Condition
T
A
= −555C to +1255C
Min
Max
Unit
Symbol
Parameter
Test Condition
SEE FIGURE 4 LOAD SWITCH AT S2 POSITION
t
PLH
Low−to−High Propagation De-
lay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
High−to−Low Propagation De-
lay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
Low−to−High Propagation De-
lay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
High−to−Low Propagation De-
lay, from (input) SCL2 or
SDA2 to (output) SCL1 or
SDA1
V
I(EN)
= 2.5 V; V
IH
= 2.5 V;
V
IL
= 0 V; V
M
= 0.75 V
V
I(EN)
= 3.3 V; V
IH
= 3.3 V;
V
IL
= 0 V; V
M
= 1.15 V
C
L
= 15 pF
C
L
= 30 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 30 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 30 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 30 pF
C
L
= 50 pF
0
0
0
0
0
0
0
0
0
0
0
0
0.6
1.2
2.0
0.75
1.5
2.0
0.6
1.2
2.0
0.75
1.5
2.5
ns
ns
t
PHL
t
PLH
t
PHL
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