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SSTUA32866EC/G,551: 产品描述Registers 1.8V 25BT-1:1/14BT-1:2 BUFFER; 产品类别逻辑逻辑; 文件大小153KB，共28页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com; 标准

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SSTUA32866EC/G,551概述

Registers 1.8V 25BT-1:1/14BT-1:2 BUFFER

SSTUA32866EC/G,551规格参数

参数名称	属性值
Brand Name	NXP Semiconductor
是否Rohs认证	符合
厂商名称	NXP(恩智浦)
零件包装代码	BGA
包装说明	13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96
针数	96
制造商包装代码	SOT-536-1
Reach Compliance Code	unknown
系列	32866
JESD-30 代码	R-PBGA-B96
长度	13.5 mm
逻辑集成电路类型	D FLIP-FLOP
湿度敏感等级	2
位数	14
功能数量	1
端子数量	96
最高工作温度	70 °C
最低工作温度
输出特性	OPEN-DRAIN
输出极性	COMPLEMENTARY
封装主体材料	PLASTIC/EPOXY
封装代码	LFBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260
传播延迟（tpd）	1.8 ns
认证状态	Not Qualified
座面最大高度	1.5 mm
最大供电电压 (Vsup)	2 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	40
触发器类型	POSITIVE EDGE
宽度	5.5 mm
最小 fmax	450 MHz

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SSTUA32866

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer

with parity for DDR2-667 RDIMM applications

Rev. 02 — 26 March 2007

Product data sheet

1. General description

The SSTUA32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2

memory modules requiring a parity checking function. It is deﬁned in accordance with the

JEDEC standard for the SSTUA32866 registered buffer. The register is conﬁgurable

(using conﬁguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in

the latter conﬁguration can be designated as Register A or Register B on the DIMM.

The SSTUA32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is deﬁned as an even

number of ones across the DIMM-independent data inputs combined with the parity input

bit.

The SSTUA32866 is packaged in a 96-ball, 6

16 grid, 0.8 mm ball pitch LFBGA package

(13.5 mm

5.5 mm).

2. Features

Conﬁgurable register supporting DDR2 up to 667 MT/s Registered DIMM applications

Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

Controlled output impedance drivers enable optimal signal integrity and speed

Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation

delay; 2.0 ns max. mass-switching)

Supports up to 450 MHz clock frequency of operation

Optimized pinout for high-density DDR2 module design

Chip-selects minimize power consumption by gating data outputs from changing state

Supports SSTL_18 data inputs

Checks parity on the DIMM-independent data inputs

Partial parity output and input allows cascading of two SSTUA32866s for correct parity

error processing

Differential clock (CK and CK) inputs

Supports LVCMOS switching levels on the control and RESET inputs

Single 1.8 V supply operation (1.7 V to 2.0 V)

Available in 96-ball, 13.5 mm

5.5 mm, 0.8 mm ball pitch LFBGA package

3. Applications

400 MT/s to 667 MT/s DDR2 registered DIMMs desiring parity checking functionality

SSTUA32866EC/G,551相似产品对比

	SSTUA32866EC/G,551	SSTUA32866EC,557	SSTUA32866EC,518	SSTUA32866EC/G-T	SSTUA32866EC518	SSTUA32866EC-G518	SSTUA32866EC557	SSTUA32866EC/G,557	SSTUA32866EC,551	SSTUA32866EC/G,518
描述	Registers 1.8V 25BT-1:1/14BT-1:2 BUFFER	IC buffer 1.8V 25bit sot536	IC buffer 1.8V 25bit sot536	寄存器 1.8V 25bt-1:7 14bt-1:2 buffer	Registers 1.8V 25BT-1:1/14BT-1:2 BUFFER	Registers 1.8V 25BT-1:7	Registers 1.8V 25BT-1:1/14BT-1:2 BUFFER	Registers 1.8V 25BT-1:1/14BT-1:2 BUFFER	Registers 1.8V 25BT-1:1/14BT-1:2 BUFFER	IC REG BUFFER 25BIT 96-LFBGA
Brand Name	NXP Semiconductor	NXP Semiconduc	NXP Semiconduc	-	-	-	-	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor
厂商名称	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)	-	-	-	-	NXP(恩智浦)	NXP(恩智浦)	NXP(恩智浦)
零件包装代码	BGA	BGA	BGA	-	-	-	-	BGA	BGA	BGA
包装说明	13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96	LFBGA, BGA96,6X16,32	LFBGA,	-	-	-	-	13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96	LFBGA,	13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96
针数	96	96	96	-	-	-	-	96	96	96
制造商包装代码	SOT-536-1	SOT536-1	SOT536-1	-	-	-	-	SOT-536-1	SOT536-1	SOT536-1
Reach Compliance Code	unknown	unknow	unknow	-	-	-	-	compliant	unknown	unknown
系列	32866	32866	32866	-	-	-	-	32866	32866	32866
JESD-30 代码	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	-	-	-	-	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96
长度	13.5 mm	13.5 mm	13.5 mm	-	-	-	-	13.5 mm	13.5 mm	13.5 mm
逻辑集成电路类型	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	-	-	-	-	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
位数	14	14	14	-	-	-	-	14	14	14
功能数量	1	1	1	-	-	-	-	1	1	1
端子数量	96	96	96	-	-	-	-	96	96	96
最高工作温度	70 °C	70 °C	70 °C	-	-	-	-	70 °C	70 °C	70 °C
输出特性	OPEN-DRAIN	OPEN-DRAIN	OPEN-DRAIN	-	-	-	-	OPEN-DRAIN	OPEN-DRAIN	OPEN-DRAIN
输出极性	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	-	-	-	-	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	-	-	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFBGA	LFBGA	LFBGA	-	-	-	-	LFBGA	LFBGA	LFBGA
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	-	-	-	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	-	-	-	-	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
传播延迟（tpd）	1.8 ns	1.8 ns	1.8 ns	-	-	-	-	1.8 ns	1.8 ns	1.8 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	-	-	-	-	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.5 mm	1.5 mm	1.5 mm	-	-	-	-	1.5 mm	1.5 mm	1.5 mm
最大供电电压 (Vsup)	2 V	2 V	2 V	-	-	-	-	2 V	2 V	2 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	-	-	-	-	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	-	-	-	-	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	-	-	-	-	YES	YES	YES
技术	CMOS	CMOS	CMOS	-	-	-	-	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	-	-	-	-	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	BALL	BALL	BALL	-	-	-	-	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	-	-	-	-	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	-	-	-	-	BOTTOM	BOTTOM	BOTTOM
触发器类型	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	-	-	-	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
宽度	5.5 mm	5.5 mm	5.5 mm	-	-	-	-	5.5 mm	5.5 mm	5.5 mm
最小 fmax	450 MHz	450 MHz	450 MHz	-	-	-	-	450 MHz	450 MHz	450 MHz

SSTUA32866EC/G,551

SSTUA32866EC/G,551概述

SSTUA32866EC/G,551规格参数

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