notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
1
IS42VM32160C
FUNCTIONAL BLOCK DIAGRAM (16Mx16)
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMH
16
2
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
16
MODE
REGISTER
13
REFRESH
CONTROLLER
DQ 0-15
SELF
REFRESH
CONTROLLER
A10
A12
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
16
DATA OUT
BUFFER
V
DD
/V
DDQ
V
ss
/V
ss
Q
16
REFRESH
COUNTER
8192
8192
8192
8192
ROW DECODER
MULTIPLEXER
13
MEMORY CELL
ARRAY
13
ROW
ADDRESS
LATCH
13
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
512
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
9
FUNCTIONAL BLOCK DIAGRAM (16Mx32)
CS
CLK
CKE
Die 01
Command
Addresses
Die 02
DQ0 –DQ31
2
Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
IS42VM32160C
PIN DESCRIPTIONS
Symbol
CLK
CKE
Type
Input
Input
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of
CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes low synchronously
with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks
are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes.
CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE
becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during
Power Down and Self Refresh modes, providing low standby power.
Bank Select: BA0 and BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge
command is being applied.
Address Inputs:A0-A12 are sampled during the BankActivate command (row address A0-A12) and Read/
Write command (column address A0-A8 with A10 defining Auto Precharge) to select one location in the
respective bank. During a Precharge command,A10 is sampled to determine if all banks are to be precharged
(A10 =HIGH).
The address inputs also provide the op-code during a Mode Register Set .
CS
Input
Chip Select:
CS enables (sampled LOW) and disables (sampled HIGH) the command decoder.All commands
are masked when
CS is sampled HIGH. CS
provides for external bank selection on systems with multiple
banks. It is considered part of the command code.
Row Address Strobe: The
RAS
signal defines the operation commands in conjunction with the
CAS
and
WE
signals and is latched at the positive edges of CLK. When
RAS
and
CS
are asserted “LOW” and
CAS
is asserted “HIGH,” either the BankActivate command or the Precharge command is selected by the WE
signal. When the
WE is asserted “HIGH,” the BankActivate command is selected and the bank designated
by BA is turned on to the active state. When the
WE
is asserted “LOW,” the Precharge command is selected
and the bank designated by BA is switched to the idle state after the precharge operation.
Column Address Strobe: The
CAS
signal defines the operation commands in conjunction with the
RAS
and
WE
signals and is latched at the positive edges of CLK. When
RAS is held “HIGH” and CS
is asserted
“LOW,” the column access is started by asserting
CAS
”LOW.” Then, the Read or Write command is selected
by asserting
WE “LOW” or “HIGH.”
Write Enable: The
WE
signal defines the operation commands in conjunction with the
RAS
and
CAS
signals
and is latched at the positive edges of CLK. The
WE
input is used to select the BankActivate or Precharge
command and Read or Write command.
Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls. The I/O buffers
are placed in a high-z state when DQM is sampled HIGH. Input data is masked when DQM is sampled
HIGH during a write cycle. Output data is masked (two-clock latency) when DQM is sampled HIGH during
a read cycle. DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0
Data I/O: The DQ0-31 input and output data are synchronized with the positive edge of CLK. The I/Os are
byte-maskable during Reads and Writes.
BA0, BA1
A0-A12
Input
Input
RAS
Input
CAS
Input
WE
Input
DQM0-3
Input
DQ0-31
Input/
Output
Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
3
IS42VM32160C
PIN CONFIGURATION
PACKAGE CODE: B 90 BALL FBGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 m Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
A4
A7
CLK
A5
A8
CKE
A6
A12
A9
NC
VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA0
CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
BA1
CS
A1
A11
RAS
DQM1 NC
VDDQ DQ8
WE
DQM0
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDDQ VSSQ DQ4
VDD
DQ0 DQ2
PIN DESCRIPTIONS
A0-A12
A0-A8
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
V
dd
Vss
V
ddq
V
ssq
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connect
4
Integrated Silicon Solution, Inc.
Rev. 00B
07/21/2010
IS42VM32160C
Mobile SDRAM Functionality
ISSI’s 512Mb Mobile SDRAMs are pin compatible and have similar functionality with ISSI’s standard SDRAMs, but
offer lower operating voltages and power saving features. For detailed descriptions of pin functions, command truth
tables, functional truth tables, device operation as well as timing diagrams please refer to ISSI document “Mobile
Synchronous DRAM Device Operations & Timing Diagrams” listed at www.issi.com
REGISTER DEFINITION
Mode Register (MR) & Extended Mode Register (EMR)
There are two mode registers in the Mobile SDRAM; Mode Register (MR) and Extended Mode Register (EMR). The
Mode Register is discussed below, followed by the Extended Mode Register. The Mode Register is used to define
the specific mode of operation of the SDRAM. This definition includes the selection of burst length, a burst type, CAS
Latency, operating mode, and a write burst mode. The mode register is programmed via the LOAD MODE REGISTER
command and will retain the stored information until it is programmed again or the device loses power.
The EMR controls the functions beyond those controlled by the MR. These additional functions are special features
of the Mobile SDRAM. They include temperature-compensated self refresh (TCSR) control, partial-array self refresh
(PASR), and output drive strength. The EMR is programmed via the MODE REGISTER SET command with BA1
= 1 and BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not
programming the extended mode register upon initialization will result in default settings for the low-power features.
The extended mode will default with the temperature sensor enabled, full drive strength, and full array (all 4 banks)
refresh.
Mode Register Definition
The MR is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure MODE
REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the device loses power.
Mode register bits M0 - M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4 -
M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10,
M11, and M12 are reserved for future use.
The mode register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.
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