19-4775; Rev 2; 5/04
IT
TION K
VALUA
E
BLE
AVAILA
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
General Description
The MAX3693 serializer is ideal for converting 4-bit-
wide, 155Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts low-voltage
differential-signal (LVDS) clock and data inputs for
interfacing with high-speed digital circuitry, and deliv-
ers a 3.3V PECL serial-data output. A fully integrated
PLL synthesizes an internal 622Mbps serial clock from
a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz ref-
erence clock.
The MAX3693 is available in the extended temperature
range (-40°C to +85°C), in a 32-pin TQFP package.
♦
Single +3.3V Supply
♦
155Mbps (4-bit-wide) Parallel to
622Mbps Serial Conversion
♦
Clock Synthesis for 622Mbps
♦
215mW Power
♦
Multiple Clock Reference Frequencies
(155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)
♦
LVDS Parallel Clock and Data Inputs
♦
Differential 3.3V PECL Serial-Data Output
Features
MAX3693
Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
PART
MAX3693ECJ
MAX3693ECJ+
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFP
32 TQFP
+Denotes
lead-free package.
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
(155MHz LVDS CRYSTAL REFERENCE)
V
CC
= +3.3V
PCLKI- PCLKI+ RCLK- RCLK+
PD0+
PD0-
OVERHEAD
GENERATION
PD1+
PD1-
PD2+
PD2-
PD3+
PD3-
PCLKO- PCLKO+
GND
V
CC
CKSET
FIL+
1µF
1µF
MAX3693
FIL-
V
CC
= +3.3V
SD- SD+
V
CC
= +3.3V
130Ω
130Ω
MAX3668
82Ω
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z
0
= 50Ω)
82Ω
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
MAX3693
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
V
CC
.......................................................................-0.5V to +5V
All Inputs, FIL+, FIL-,
PCLKO+, PCLKO- ..............................-0.5V to (V
CC
+ 0.5V)
Output Current
LVDS Outputs (PCLKO±)................................................10mA
PECL Outputs (SD±).......................................................50mA
Continuous Power Dissipation (T
A
= +85°C)
TQFP (derate 10.20mW/°C above +85°C) ...................663mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3V to +3.6V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ±1% to (V
CC
- 2V), T
A
= -40°C to +85°C, unless other-
wise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C.)
PARAMETER
Supply Current
PECL OUTPUTS (SD±)
Output High Voltage
Output Low Voltage
V
OH
V
OL
T
A
= 0°C to +85°C
T
A
= -40°C
T
A
= 0°C to +85°C
T
A
= -40°C
Differential input voltage =
100mV
Common-mode voltage =
50mV
V
CC
- 1.025
V
CC
- 1.085
V
CC
- 1.81
V
CC
-1.83
V
CC
- 0.88
V
CC
- 0.88
V
CC
- 1.62
V
CC
- 1.555
V
V
SYMBOL
I
CC
CONDITIONS
PECL outputs unterminated
MIN
38
TYP
65
MAX
100
UNITS
mA
LVDS INPUTS AND OUTPUTS (PCLKI±, RCLK±, PCLKO±, PD_±)
Input Voltage Range
Differential Input Threshold
Threshold Hysteresis
Differential Input Resistance
Output High Voltage
Output Low Voltage
Differential Output Voltage
Change in Magnitude of Differential Output
Voltage for Complementary States
Output Offset Voltage
Change in Magnitude of Output Offset Voltage
for Complementary States
Single-Ended Output Resistance
Change in Magnitude of Single-Ended Output
Resistance for Complementary Outputs
PROGRAMMING INPUT (CKSET)
CKSET Input Current
I
CKSET
CKSET = 0 or V
CC
±500
µA
V
I
V
IDTH
V
HYST
R
IN
V
OH
V
OL
|V
OD
|
∆|V
OD
|
V
OS
∆V
OS
R
O
∆R
O
40
95
±2.5
1.125
0.925
250
400
±25
1.275
±25
140
±10
85
0
-100
60
100
115
1.475
2.4
100
V
mV
mV
Ω
V
V
mV
mV
V
mV
Ω
%
2
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3V to +3.6V, differential LVDS load = 100Ω ±1%, PECL loads = 50Ω ±1% to (V
CC
- 2V), T
A
= -40°C to +85°C, unless other-
wise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C.) (Note 1)
PARAMETER
Serial Clock Rate
Parallel Data-Setup Time
Parallel Data-Hold Time
PCLKO to PCLKI Skew
Output Random Jitter
PECL Differential Output
Rise/Fall Time
SYMBOL
f
SCLK
t
SU
t
H
t
SKEW
Φ
0
t
R,
t
F
200
T
A
= +25°C
200
600
0
+4.0
11
CONDITIONS
MIN
TYP
622.08
MAX
UNITS
MHz
ps
ps
ns
ps
RMS
ps
MAX3693
Note 1:
AC characteristics guaranteed by design and characterization.
Typical Operating Characteristics
(V
CC
= +3.3V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ±1% to (V
CC
- 2V), T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX3693-01
PARALLEL DATA-SETUP TIME
vs. TEMPERATURE
MAX3693-02
PARALLEL DATA-HOLD TIME
vs. TEMPERATURE
MAX3693-03
100
200
PARALLEL DATA-SETUP TIME (ps)
250
PARALLEL DATA-HOLD TIME (ps)
80
SUPPLY CURRENT (mA)
150
200
60
100
150
40
50
100
20
PECL OUTPUTS UNTERMINATED
0
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
0
50
-50
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
0
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
MAX3693
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ±1% to (V
CC
- 2V), T
A
= +25°C, unless otherwise noted.)
SERIAL-DATA OUTPUT EYE DIAGRAM
MAX3693-05
SERIAL-DATA OUTPUT JITTER
MAX3693-06
1.1V
1.0042V
57mV/
div
10mV/
div
f
RCLK
= 155.52MHz
0.536V
200ps/div
0.904V
Mean 25.22ns
RMS
∆
4.073ps
PkPk 32.6ps
10ps/div
µ
±1
σ
70.373%
µ
±2
σ
95.357%
µ
±3
σ
99.759%
Pin Description
PIN
1, 3, 5, 7
2, 4, 6, 8
9, 17, 18, 19,
24, 25, 32
10
11
12, 13, 16,
21, 28, 29
14
15
NAME
PD0+ to PD3+
PD0- to PD3-
GND
PCLKO-
PCLKO+
V
CC
SD-
SD+
FUNCTION
Noninverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
Inverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
Ground
Inverting LVDS Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead man-
agement circuit.
Noninverting LVDS Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead
management circuit.
+3.3V Supply Voltage
Inverting PECL Serial-Data Output
Noninverting PECL Serial-Data Output
Reference Clock Rate Programming Pin.
CKSET = V
CC
: Reference Clock Rate = 155.52MHz
CKSET = Open: Reference Clock Rate = 77.76MHz
CKSET = 20kΩ to GND: Reference Clock Rate = 51.84MHz
CKSET = GND Reference Clock Rate = 38.88MHz
Filter Capacitor Input. See
Typical Operating Circuit
for external-component connections.
Filter Capacitor Input. See
Typical Operating Circuit
for external-component connections.
Noninverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to
the RCLK inputs.
Inverting LVDS Reference Clock Input. Connect an LVDS-compatible crystal reference clock to the
RCLK inputs.
Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the
PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
Inverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI
inputs. Note that data is updated on the positive transition of the PCLKI signal.
20
CKSET
22
23
26
27
30
31
4
FIL-
FIL+
RCLK+
RCLK-
PCLKI+
PCLKI-
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
with Clock Synthesis and LVDS Inputs
_______________Detailed Description
The MAX3693 serializer comprises a 4-bit parallel input
register, a 4-bit shift register, control and timing logic, a
PECL output buffer, LVDS input/output buffers, and a
frequency-synthesizing PLL (consisting of a phase/
frequency detector, loop filter/amplifier, voltage-
controlled oscillator, and prescaler). This device con-
verts 4-bit-wide, 155Mbps data to 622Mbps serial data
(Figure 1).
The PLL synthesizes an internal 622Mbps reference
used to clock the output shift register. This clock is
generated by locking onto the external 155.52MHz,
77.76MHz, 51.84MHz, or 38.88MHz reference-clock
signal (RCLK).
The incoming parallel data is clocked into the
MAX3693 on the rising transition of the parallel-clock-
input signal (PCLKI). The control and timing logic
ensure proper operation if the parallel-input register is
latched within a window of time that is defined with
respect to the parallel-clock-output signal (PCLKO).
PCLKO is the synthesized 622Mbps internal serial-
clock signal divided by four. The allowable PCLKO-to-
PCLKI skew is 0 to +4ns. This defines a timing window
at about the PCLKO rising edge, during which
a PCLKI rising edge may occur (Figure 2).
MAX3693
PD3+
PD3-
LVDS
MAX3693
4-BIT
PARALLEL
INPUT
REGISTER
PD2+
PD2-
LVDS
PD1+
PD1-
LVDS
PD0+
PD0-
LVDS
PCLKI+
LVDS
PCLKI-
PRESCALER
SHIFT
4-BIT
SHIFT
REGISTER
PECL
SD+
SD-
RCLK+
LVDS
RCLK-
PHASE/FREQ
DETECT
VCO
CONTROL
LATCH
LVDS
FIL+ FIL- CKSET
PCLKO+ PCLKO-
Figure 1. Functional Diagram
_______________________________________________________________________________________
5
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
