VS-ST650C..L Series
www.vishay.com
Vishay Semiconductors
Phase Control Thyristors
(Hockey PUK Version), 790 A
FEATURES
• Center amplifying gate
• Metal case with ceramic insulator
• International standard case B-PUK (TO-200AC)
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
TYPICAL APPLICATIONS
• DC motor control
B-PUK (TO-200AC)
• Controlled DC power supplies
• AC controllers
PRIMARY CHARACTERISTICS
I
T(AV)
V
DRM
/V
RRM
V
TM
I
GT
T
J
Package
Circuit configuration
790 A
2000 V, 2200 V, 2400 V
2.07 V
100 mA
-40 °C to +125 °C
B-PUK (TO-200AC)
Single SCR
MAJOR RATINGS AND CHARACTERISTICS
PARAMETER
I
T(AV)
I
T(RMS)
I
TSM
I
2
t
V
DRM
/V
RRM
t
q
T
J
Typical
T
hs
T
hs
50 Hz
60 Hz
50 Hz
60 Hz
TEST CONDITIONS
VALUES
790
55
1557
25
10 100
10 700
510
475
2000 to 2400
200
-40 to +125
UNITS
A
°C
A
°C
A
kA
2
s
V
μs
°C
ELECTRICAL SPECIFICATIONS
VOLTAGE RATINGS
TYPE NUMBER
VOLTAGE
CODE
20
VS-ST650C..L
22
24
V
DRM
/V
RRM
, MAXIMUM REPETITIVE
PEAK AND OFF-STATE VOLTAGE
V
2000
2200
2400
V
RSM
, MAXIMUM
NON-REPETITIVE PEAK VOLTAGE
V
2100
2300
2500
80
I
DRM
/I
RRM
MAXIMUM
AT T
J
= T
J
MAXIMUM
mA
Revision: 21-Sep-17
Document Number: 93738
1
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-ST650C..L Series
www.vishay.com
Vishay Semiconductors
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Maximum average on-state current
at heatsink temperature
Maximum RMS on-state current
Maximum peak, one-cycle
non-repetitive surge current
SYMBOL
I
T(AV)
I
T(RMS)
TEST CONDITIONS
180° conduction, half sine wave
Double side (single side) cooled
DC at 25 °C heatsink temperature double side cooled
t = 10 ms
I
TSM
t = 8.3 ms
t = 10 ms
t = 8.3 ms
t = 10 ms
Maximum I
2
t for fusing
I
2
t
t = 8.3 ms
t = 10 ms
t = 8.3 ms
Maximum I
2
t
for fusing
Low level value of threshold voltage
High level value of threshold voltage
Low level value of on-state slope
resistance
High level value of on-state
slope resistance
Maximum on-state voltage
Maximum holding current
Typical latching current
I
2
t
V
T(TO)1
V
T(TO)2
r
t1
r
t2
V
TM
I
H
I
L
No voltage
reapplied
100 % V
RRM
reapplied
No voltage
reapplied
100 % V
RRM
reapplied
VALUES
790 (324)
55 (85)
1857
10 100
10 700
8600
Sinusoidal half wave,
initial T
J
= T
J
maximum
9150
510
475
370
347
5100
1.04
1.13
0.61
m
(I >
x I
T(AV)
), T
J
= T
J
maximum
I
pk
= 1700 A, T
J
= T
J
maximum, t
p
= 10 ms sine pulse
T
J
= 25 °C, anode supply 12 V resistive load
0.35
2.07
600
1000
V
mA
kA
2
s
V
kA
2
s
A
UNITS
A
°C
t = 0.1 to 10 ms, no voltage reapplied
(16.7 % x
x I
T(AV)
< I <
x I
T(AV)
), T
J
= T
J
maximum
(I >
x I
T(AV)
), T
J
= T
J
maximum
(16.7 % x
x I
T(AV)
< I <
x I
T(AV)
), T
J
= T
J
maximum
SWITCHING
PARAMETER
Maximum non-repetitive rate of
rise of turned-on current
Typical delay time
Maximum turn-off time
SYMBOL
dI/dt
t
d
t
q
TEST CONDITIONS
Gate drive 20 V, 20
,
t
r
1 μs
T
J
= T
J
maximum, anode voltage
80 % V
DRM
Gate current 1 A, dI
g
/dt = 1 A/μs
V
d
= 0.67 % V
DRM
, T
J
= 25 °C
I
TM
= 750 A, T
J
= T
J
maximum, dI/dt = 60 A/μs
V
R
= 50, dV/dt = 20 V/μs, Gate 0 V 100
,
t
p
= 500 μs
VALUES
1000
1.0
μs
200
UNITS
A/μs
BLOCKING
PARAMETER
Maximum critical rate of rise of off-state voltage
Maximum peak reverse and off-state leakage
current
SYMBOL
dV/dt
I
RRM
,
I
DRM
TEST CONDITIONS
T
J
= T
J
maximum linear to 80 % rated V
DRM
T
J
= T
J
maximum, rated V
DRM
/V
RRM
applied
VALUES
500
80
UNITS
V/μs
mA
Revision: 21-Sep-17
Document Number: 93738
2
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-ST650C..L Series
www.vishay.com
Vishay Semiconductors
VALUES
TYP. MAX.
10.0
2.0
3.0
T
J
= T
J
maximum, t
p
5 ms
T
J
= -40 °C
200
Maximum required gate trigger/
current/voltage are the lowest
value which will trigger all units
12 V anode to cathode applied
100
50
2.5
1.8
1.1
Maximum gate current/voltage
not to trigger is the maximum
value which will not trigger any
unit with rated V
DRM
anode to
cathode applied
10
0.25
20
5.0
-
200
-
-
3.0
-
mA
V
V
mA
T
J
= 25 °C
T
J
= 125 °C
T
J
= -40 °C
TRIGGERING
PARAMETER
Maximum peak gate power
Maximum average gate power
Maximum peak positive gate current
Maximum peak positive gate voltage
Maximum peak negative gate voltage
DC gate current required to trigger
SYMBOL
P
GM
P
G(AV)
I
GM
+ V
GM
- V
GM
I
GT
TEST CONDITIONS
T
J
= T
J
maximum, t
p
5 ms
T
J
= T
J
maximum, f = 50 Hz, d% = 50
UNITS
W
A
V
DC gate voltage required to trigger
DC gate current not to trigger
DC gate voltage not to trigger
V
GT
I
GD
V
GD
T
J
= 25 °C
T
J
= 125 °C
T
J
= T
J
maximum
THERMAL AND MECHANICAL SPECIFICATIONS
PARAMETER
Maximum operating temperature range
Maximum storage temperature range
Maximum thermal resistance, junction to heatsink
Maximum thermal resistance, case to heatsink
Mounting force, ± 10 %
Approximate weight
Case style
See dimensions - link at the end of datasheet
SYMBOL
T
J
T
Stg
R
thJ-hs
R
thC-hs
DC operation single side cooled
DC operation double side cooled
DC operation single side cooled
DC operation double side cooled
TEST CONDITIONS
VALUES
-40 to 125
-40 to 150
0.073
0.031
0.011
0.006
14 700
(1500)
255
N
(kg)
g
K/W
UNITS
°C
B-PUK (TO-200AC)
R
thJ-hs
CONDUCTION
CONDUCTION ANGLE
180°
120°
90°
60°
30°
SINUSOIDAL CONDUCTION
SINGLE SIDE
0.009
0.011
0.014
0.020
0.036
DOUBLE SIDE
0.009
0.011
0.014
0.020
0.036
RECTANGULAR CONDUCTION
SINGLE SIDE
0.006
0.011
0.015
0.021
0.036
DOUBLE SIDE
0.006
0.011
0.015
0.021
0.036
T
J
= T
J
maximum
K/W
TEST CONDITIONS
UNITS
Note
• The table above shows the increment of thermal resistance R
thJ-hs
when devices operate at different conduction angles than DC
Revision: 21-Sep-17
Document Number: 93738
3
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-ST650C..L Series
www.vishay.com
Vishay Semiconductors
1 30
M a x im u m A llo w a b le H e a tsin k Te m p e ra tu re (° C )
1 30
M a x im u m A llo w a b le H e a t sin k T e m p e ra t u re ( °C )
1 20
1 10
1 00
90
80
70
60
0
50
1 00 1 50 20 0 2 5 0 3 0 0 35 0 4 00
A v e ra g e O n -s ta t e C u rre n t (A )
30°
60 °
9 0°
1 2 0°
1 8 0°
C o nduc tion An g le
ST 6 5 0 C ..L Se rie s
(Sin g le Sid e C o o le d )
R
th J-hs
(D C ) = 0 .0 7 3 K / W
1 20
1 10
1 00
90
80
70
60
50
40
30
20
0
2 00
4 00
30°
S T 6 5 0 C ..L S e rie s
(D o u b le S id e C o o le d )
R
th J-hs
(D C ) = 0 .0 3 1 K / W
Co nd uc tio n Pe rio d
9 0°
6 0°
1 2 0°
180 °
60 0
DC
80 0 10 0 0 1 2 00 1 40 0
A v e ra g e O n -st a t e C u rre n t (A )
Fig. 1 - Current Ratings Characteristics
Fig. 4 - Current Ratings Characteristics
13 0
M a xim u m A llo w a b le H e a t sin k T e m p e ra t u re (°C )
12 0
11 0
10 0
90
80
70
60
50
40
30
20
0
10 0 2 00 3 0 0 4 0 0 5 00 6 00 7 0 0 80 0
A v e ra g e O n - sta t e C u rre n t (A )
60 °
30°
90°
1 8 0°
1 2 0°
C o nduc tion A ng le
M a xim u m A v e ra g e O n -st a te P o w e r Lo ss (W )
ST 6 5 0 C ..L Se rie s
(D o u ble S id e C o o le d )
R
thJ-h s
(D C ) = 0 .0 3 1 K / W
20 0 0
17 5 0
15 0 0
12 5 0
10 0 0
750
500
250
0
0
1 0 0 2 00 3 0 0 4 0 0 50 0 6 0 0 70 0 8 00
A v e ra g e O n -st a t e C u rre n t (A )
C o nd uc tio n A ng le
1 8 0°
1 2 0°
90°
60°
30°
R M S Lim it
S T 6 5 0 C ..L S e rie s
T
J
= 1 2 5°C
Fig. 2 - Current Ratings Characteristics
Fig. 5 - On-State Power Loss Characteristics
13 0
M a xim u m A llo w a b le H e a t sin k T e m p e ra t u re (°C )
M ax im u m A v e ra g e O n - st a t e P o w e r Lo ss (W )
12 0
11 0
10 0
90
80
70
60
50
40
30
20
0
10 0 2 00 3 0 0 4 0 0 5 00 6 00 7 0 0 80 0
A v e ra g e O n - sta t e C u rre n t (A )
60 °
30°
90°
1 8 0°
1 2 0°
C o nduc tion A ng le
ST 6 5 0 C ..L Se rie s
(D o u ble S id e C o o le d )
R
thJ-h s
(D C ) = 0 .0 3 1 K / W
2 40 0
2 20 0
2 00 0
1 80 0
1 60 0
DC
1 8 0°
1 2 0°
90°
60°
30°
1 40 0
R M S Lim it
1 20 0
1 00 0
8 00
6 00
4 00
2 00
0
0
20 0
4 00
600
80 0 10 0 0 1 20 0 1 4 00
A v e ra g e O n -st a te C urre n t (A )
S T 6 5 0 C ..L S e rie s
T
J
= 1 2 5°C
C o ndu ct io n P erio d
Fig. 3 - Current Ratings Characteristics
Fig. 6 - On-State Power Loss Characteristics
Revision: 21-Sep-17
Document Number: 93738
4
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
VS-ST650C..L Series
www.vishay.com
Vishay Semiconductors
1 2 00 0
In itia l T
J
= 1 2 5°C
@ 6 0 H z 0 .0 0 8 3 s
@ 5 0 H z 0 .0 1 0 0 s
P e a k H a lf Sin e W a v e O n -st a t e C u rre n t (A )
10 0 00
P e a k H a lf Sin e W a v e O n -st a te C u rre n t (A )
9 00 0
8 00 0
7 00 0
6 00 0
5 00 0
A t A ny R at e d L o a d C o nd itio n A n d W ith
R at e d V
RR M
A p plie d Fo llo w in g Su rge .
M a x im u m N o n R e p e t it iv e S u rg e C u rre n t
V e rsu s P u lse T ra in D u ra tio n . C o n t ro l
1 1 00 0
O f C o n d u c t io n M a y N o t B e M a in t a in e d .
In it ia l T
J
= 1 2 5 °C
1 0 00 0
N o V o lt a g e R e a p p lie d
R a te d V
R RM
Re a p p lie d
90 0 0
80 0 0
70 0 0
60 0 0
50 0 0
S T6 5 0 C ..L S e rie s
ST 6 5 0 C ..L S e r ie s
4 00 0
1
10
10 0
Nu m be r O f Equ al Am p litud e H alf C yc le C urren t Pulse s (N )
40 0 0
0 .0 1
0. 1
P u lse T ra in D u ra t io n (s)
1
Fig. 7 - Maximum Non-Repetitive Surge Current
Single and Double Side Cooled
Fig. 8 - Maximum Non-Repetitive Surge Current
Single and Double Side Cooled
10000
Instan tan eous On -stat e Current (A)
T
J
= 25°C
1000
T = 125°C
J
ST650C..L Series
100
0. 5
1
1.5
2
2.5
3
Instan tan eous O n -stat e V oltage (V )
Fig. 9 - On-State Voltage Drop Characteristics
0. 1
T ra n sie n t T h e rm a l Im pe d a nc e Z
thJ- hs
(K / W )
St e a d y St a te V a lu e
R
thJ-hs
= 0 .0 7 3 K/ W
(Sin gle Sid e C o o le d)
R
thJ-hs
= 0 .0 3 1 K/ W
( D o u ble Sid e C o o le d )
0 .0 1
( D C O p e ra t io n )
ST 6 5 0 C ..L Se rie s
0 .0 0 1
0 .00 1
0.0 1
0 .1
S q ua re W a v e P u lse D u ra t io n ( s)
1
10
Fig. 10 - Thermal Impedance Z
thJ-hs
Characteristics
Revision: 21-Sep-17
Document Number: 93738
5
For technical questions within your region:
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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