AS4C16M32MD1
512M (16M x32 bit) Mobile DDR SDRAM
Confidential
(Rev. 1.0, July. /2014)
LPDDR MEMORY
512M (16Mx32bit)
Mobile DDR SDRAM
Revision History
Revision No
1.0
Initial Release
Description
Date
2014/07/18
AS4C16M32MD1
512M (16M x32 bit) LP Mobile DDR SDRAM
Confidential
(Rev. 1.0, July. /2014)
1. FEATURES
•
Density :
512Mbit
•
Data width:
x32
•
Power supply :
VDD, VDDQ = 1.7 to 1.95V
•
Speed
- Clock frequency : 200MHz (max.)
- Data rate : 400Mbps (max.)
•
Four internal banks for concurrent
operation
•
Interface :
LVCMOS
•
Burst lengths (BL)
: 2, 4, 8, 16
•
Burst type (BT)
- Sequential : 2, 4, 8, 16
- Interleave : 2, 4, 8, 16
•
CAS# latency (CL)
: 3
•
Precharge :
auto precharge option for each
burst access
•
Driver strength :
normal, 1/2, 1/4, 1/8
•
Refresh :
auto-refresh, self-refresh
•
Refresh cycles :
8192 cycles/64ms
- Average refresh period : 7.8us
•
Operating temperature range
- Commercial (Extended) -25°C to +85°C
- Industrial -40°C to +85°C
Package:
90-ball FPBGA (8x13.0mm)
All parts are ROHS Compliant
•
Low power consumption
•
Partial Array Self-Refresh (PASR)
•
Auto Temperature Compensated Self-Refresh
(ATCSR) by built-in temperature sensor
•
Deep power down mode(DPD Mode)
•
Burst termination by burst stop command and
precharge command
•
DDL is not implemented
•
Double-data-rate architecture :
Two data transfers per one clock cycle
•
The high speed data transfer is realized by the
2bits prefetch pipelined architecture
•
Bi-directional data strobe (DQS) is transmitted/
received with data for capturing data at the
receiver
•
DQS is edge-aligned with data for READs;
center-aligned with data for WRITEs
•
Differential clock inputs (CK and CK#)
•
Commands entered on each positive CK edge;
data and data mask referenced to both edges
of DQS
•
Data mask (DM) for write data
•
Clock Stop capability during idle periods
Confidential
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AS4C16M32MD1
2. GENERAL DESCRIPTION
This AS4C16M32MD1 is 536,870,912 bits synchronous double data rate Dynamic RAM. Each
134,217,728 bits bank is organized as 8,192 rows by 1024 columns by 16 bits or 8,192 rows by 512
columns by 32bits, fabricated with Alliance Memory’s
high performance CMOS technology. This device
uses double data rate architecture to achieve high- speed operation. The double data rate architecture
is essentially 2n-prefetch architecture with an interface designed to transfer two data words per clock
cycle at the I/O balls. Range of operating frequencies, programmable burst lengths and programmable
latencies allow the same device to be useful for a variety of high bandwidth and high performance
memory system applications.
Table 1. Speed Grade Information
Speed Grade – Data rate Clock Frequency
400Mbps (max)
200 MHz (max)
CAS Latency
3
t
RCD
(ns)
15
t
RP
(ns)
15
Table 2 – Ordering Information for ROHS Compliant Products
Product part No
AS4C16M32MD1-5BCN
Org
16M x 32
Temperature
Commercial
(Extended)
-25°C to 85°C
Industrial
-40°C to 85°C
Max Clock (MHz)
200
Package
90-ball FBGA
AS4C16M32MD1-5BIN
16M x 32
200
90-ball FBGA
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AS4C16M32MD1
2.1 Package Pin Configurations
Figure 2.2 Pin configurations
< Top View >
Confidential
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Rev. 1.0/July 2014
AS4C16M32MD1
2.3 Pin Description
CK, CK# (input pins)
Clock: The CK and the CK# are the differential clock inputs. All address and control input signals are
samples on the crossing of the positive edge of CK and negative edge of CK. Input and output data
is referenced to the cross of CK and CK# (both directions of crossing). Internal signals are derived
from CK/CK#.
CKE (Input pins)
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and device input
buffers and output drivers. Taking CKE LOW provides PRE-CHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is
synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously.
Input buffers, excluding CK, CK# and CKE are disabled during power-down and self-refresh mode
which are contrived for low standby power consumption.
CS# (input pin)
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All
commands are masked when CS# is registered HIGH. CS# provides for external bank selection on
systems with multiple banks. CS# is considered part of the command code.
RAS#, CAS#, and WE# (input pins)
Command Inputs: These pins define operating commands (read, write, etc.) depending on the
combinations of their voltage levels. See "Command operation".
LDM, UDM (input pins) for x32 DM0-DM3
Input Data Mask: Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input-only, the DM loading matches the DQ and DQS loading.
For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1
corresponds to the data on DQ8-DQ15, DM2 corresponds to the data on
DQ16-DQ23, and DM3 corresponds to the data on DQ24-DQ31.
BA0, BA1 (input pins)
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
A0 [n:0] (input pins)
Address Inputs: provide the row address for ACTIVE commands, and the column address and AUTO
PRECHARGE bit for READ / WRITE commands, to select one location out of the memory array in the
respective bank. The address inputs also provide the op-code during a MODE REGISTER SET command.
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Rev. 1.0/July 2014
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