) ..............................................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical
Operating Circuit,
V+ = 2.25V to 3.6V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V+ = 3.3V, T
A
= +25°C.)
(Note 1)
PARAMETER
Operating Supply Voltage
Output Load External Supply
Voltage P0–P9
Standby Current
(Interface Idle)
SYMBOL
V+
V
EXT
All digital inputs at V+
or GND
f
SCLK
= 26MHz; other
digital inputs at V+ or
GND; DOUT unloaded
T
A
= +25°C
T
A
= T
MIN
to +85°C
T
A
= T
MIN
to T
MAX
T
A
= +25°C
T
A
= T
MIN
to +85°C
T
A
= T
MIN
to T
MAX
0.7 x V+
0.3 x V+
-0.2
(Note 2)
V
OLP
_
I
SINK
= 0.5mA, output register set to 0x00
V
OLPOUT
= 5V
V
OHDOUT
V
OLDOUT
V
POR
I
SOURCE
= -6mA
I
SINK
= 6mA
2
V+ - 0.3V
0.3
10.8
10
0.4
20
+0.2
385
Supply Current
Input High Voltage
(P0–P9, DIN, SCLK,
CS)
Input Low Voltage
(P0–P9, DIN, SCLK,
CS)
Input Leakage Current
(P0–P9, DIN, SCLK,
CS)
Input Capacitance
(P0–P9, DIN, SCLK,
CS
Output Low Voltage (P0–P9)
Output Low Short-Circuit Current
(P0–P9)
Output High Voltage (DOUT)
Output Low Voltage (DOUT)
Power-On Reset Voltage
I+
0.70
CONDITIONS
MIN
2.25
TYP
MAX
3.60
7
1.5
1.7
1.9
620
680
730
V
V
µA
pF
V
mA
V
V
V
µA
µA
UNITS
V
V
I
STBY
V
IH
V
IL
I
IH
, I
IL
P0–P9 output register set to 0x01
P0–P9 output register set to 0x01
2
Maxim Integrated
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
TIMING CHARACTERISTICS
(Typical
Operating Circuit,
V+ = 2.25V to 3.6V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V+ = 3.3V, T
A
= +25°C.)
(Note 1)
PARAMETER
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall to SCLK Rise Setup
SCLK Rise to
CS
Rise Hold
DIN Setup Time
DIN Hold Time
Output Data Propagation Delay
DOUT Output Rise and Fall
Times
Minimum
CS
Pulse High
SYMBOL
t
CP
t
CH
t
CL
t
CSS
t
CSH
t
DS
t
DH
t
DO
t
FT
t
CSW
C
LOAD
= 20pF (Note 2)
38.4
CONDITIONS
MIN
38.4
19
19
9.5
2.5
9.5
2.5
19
10
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1:
All parameters are tested at T
A
= +25°C. Specifications over temperature are guaranteed by design.
Note 2:
Guaranteed by design.
MAX7317 Block Diagram
MAX7317
I/O REGISTER
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
I/O PORTS
SCLK
CS
DIN
DOUT
4-WIRE SERIAL INTERFACE
Maxim Integrated
3
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
Typical Operating Characteristics
(T
A
= +25°C, unless otherwise noted.)
PORT SINK CURRENT
vs. PORT VOLTAGE
MAX7317 toc01
STANDBY CURRENT
vs. TEMPERATURE
MAX7317 toc02
SUPPLY CURRENT (I+)
vs. TEMPERATURE
MAX7317 toc03
15
T
A
= -40°C
PORT SINK CURRENT (mA)
12
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
6
1.0
0.9
STANDBY CURRENT (µA)
V+ = 3.6V
0.8
V+ = 3.3V
0.7
0.6
0.5
0.4
V+ = 2.25V
V+ = 2.7V
0.5
V+ = 3.3V
V+ = 3.6V
STANDBY CURRENT (mA)
0.4
9
0.3
0.2
V+ = 2.7V
0.1
V+ = 2.25V
3
0
0
2
4
PORT VOLTAGE (V)
6
8
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Pin Description
PIN
QSOP
1
2
QFN
15
16
NAME
SCLK
CS
FUNCTION
Serial-Clock Input. On SCLK’s rising edge, data shifts into the internal shift register. On
SCLK’s falling edge, data is clocked out of DOUT. SCLK is active only while
CS
is low.
Chip-Select Input. Serial data is loaded into the shift register while
CS
is low. The most recent
16 bits of data latch on
CS’s
rising edge.
I/O Ports. P0 to P9 can be configured as open-drain, current-sink outputs rated at 20mA
maximum, or as CMOS inputs, or as open-drain outputs. Loads should be connected to a
supply voltage no higher than 7V.
Ground
Serial-Data Output. The data into DIN is valid at DOUT 15.5 clock cycles later. Use this pin to
daisy-chain several devices or allow data readback. Output is push-pull.
Serial-Data Input. Data from DIN loads into the internal 16-bit shift register on SCLK’s rising
edge.
Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic capacitor.
Exposed Pad on Package Underside. Connect to GND.
3–7, 9–13
8
14
15
16
—
1–5, 7–11
6
12
13
14
PAD
P0–P9
GND
DOUT
DIN
V+
Exposed
pad
4
Maxim Integrated
MAX7317
10-Port SPI-Interfaced I/O Expander with
Overvoltage and Hot-Insertion Protection
Detailed Description
The MAX7317 is a general-purpose input/output (GPIO)
peripheral that provides 10 I/O ports, P0 to P9, con-
trolled through a high-speed SPI-compatible serial
interface. The 10 I/O ports can be used as inputs or
open-drain outputs in any combination. Ports withstand
7V independent of the MAX7317’s supply voltage
whether used as inputs or outputs.
Figure 1 shows the I/O port structure of the MAX7317.
same value with a single command by writing the same
data to multiple output registers.
Serial Interface
The MAX7317 communicates through an SPI-compati-
ble 4-wire serial interface. The interface has three
inputs: clock (SCLK), chip select (CS),
and data in
(DIN), and one output, data out (DOUT).
CS
must be
low to clock data into or out of the device, and DIN
must be stable when sampled on the rising edge of
SCLK. DOUT is stable on the rising edge of SCLK.
SCLK and DIN can be used to transmit data to other
peripherals. The MAX7317 ignores all activity on SCLK
and DIN except when
CS
is low.
Note that the SPI protocol expects DOUT to be high
impedance when the MAX7317 is not being accessed;
DOUT on the MAX7317 is never high impedance. Go to
www.maxim-ic.com/an1879 for ways to convert the
MAX7317 to tri-state, if required.
Register Structure
The MAX7317 contains 10 internal registers, addressed
as 0x00–0x09, which control the peripheral (Table 2).
Two further addresses, 0x0E and 0x0F, do not store
data but return the port input status when read. Four
virtual addresses, 0x0A–0x0D, allow more than one
register to be written with the same data to simplify soft-
ware. The RAM register provides 1 byte of memory that
can be used for any purpose. The no-op address,
0x20, causes no action when written or read, and is
used as a dummy register when accessing one
MAX7317 out of multiple cascaded devices.
Initial Power-Up
On power-up, all control registers are reset (Table 2).
Power-up status sets I/O ports P0 to P9 high imped-
ance, and puts the device into shutdown mode.
Control and Operation Using
the 4-Wire Interface
Controlling the MAX7317 requires sending a 16-bit
word. The first byte, D15 through D8, is the command,
and the second byte, D7 through D0, is the data byte
(Table 5).
RAM Register
The RAM register provides a byte of memory that can
be used for any purpose.
GPIO Port Direction Configuration
The 10 I/O ports P0 through P9 can be configured to
any combination of inputs and outputs. Ports withstand
7V independent of the MAX7317’s supply voltage,
whether used as inputs or outputs. Configure a port as
an input by setting its output register to 0x01, which
sets the port output high impedance (Table 4).
DATA FROM
SHIFT REGISTER
D
OUTPUT
PORT REGISTER
Q
FF
WRITE PULSE
CK
Q
N
OUTPUT PORT
REGISTER DATA
I/O PIN
Input Port Registers
Reading an input port register returns the logic levels at
the I/O port pins. The input port registers are read only.
A write to an input port register is ignored.
INPUT
PORT REGISTER
D
FF
READ PULSE
CK
Q
Q
INPUT PORT
REGISTER DATA
GND
Output Registers
The MAX7317 uses one 8-bit register to control each
output port (Table 4). Each port can be configured as
an input or open-drain output. Write 0x00 to the output
register to set the port as a logic-low output, or 0x01 to
set the port as a logic-high output or logic input.
The 10 registers, 0x00 through 0x09, control an I/O port
each (Table 4). Four pseudo-register addresses, 0x0A
through 0x0D, allow groups of outputs to be set to the
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